Charge-pump reducing current mismatch in DLLs and PLLs. - Kyung-Soo Ha; Lee-Sup Kim (ISCAS, 2006)

A 0.18µm CMOS 10Gb/s 1: 4 DEMUX using replica-bias circuits for optical receiver. - Ju-Pyo Hong; Kyung-Soo Ha; Lee-Sup Kim (ISCAS, 2006)

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (ISSCC, 2009)

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (IEEE J. Solid State Circuits, 2009)

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. - Ji-Hwan Seol; Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Joo-Sun Choi; Lee-Sup Kim (ISSCC, 2013)

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. - Tae-Young Oh; Hoeju Chung; Young-Chul Cho; Jang-Woo Ryu; Kiwon Lee; Changyoung Lee; Jin-Il Lee; Hyoung-Joo Kim 002; Min-Soo Jang; Gong-Heum Han; Kihan Kim; Daesik Moon; et al. (ISSCC, 2014)

A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. - Sang-Hye Chung; Young-Ju Kim 001; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. - Tae-Young Oh; Hoeju Chung; Jun-Young Park; Ki-Won Lee; Seung-Hoon Oh; Su-Yeon Doo; Hyoung-Joo Kim 002; ChangYong Lee; Hye-Ran Kim; Jong-Ho Lee; Jin-Il Lee; Kyung-Soo Ha; et al. (IEEE J. Solid State Circuits, 2015)

A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. - Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. - Hye-Yoon Joo; Seung-Jun Bae; Young-Soo Sohn; Young-Sik Kim; Kyung-Soo Ha; Min-Su Ahn; Young-Ju Kim 001; Yong-Jun Kim; Ju-Hwan Kim; Won-Jun Choi; Chang-Ho Shin; Soo Hwan Kim; et al. (ISSCC, 2016)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)