A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. - Taek-Joon An; Kyung-Sub Son; Young-Jin Kim; In-Seok Kong; Jin-Ku Kang (ISCAS, 2014)

A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection. - Taek-Joon Ahn; Kyung-Sub Son; Yong-Sung Ahn; Jin-Ku Kang (IEICE Electron. Express, 2014)

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS. - Kyongsu Lee; Youngjin Kim; Kyung-Sub Son; Sangmin Lee; Jin-Ku Kang (IEICE Electron. Express, 2014)

On-chip jitter tolerance measurement technique for CDR circuits. - Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (ISCAS, 2015)

Precise time-difference repetition for TDC with delay mismatch cancelling scheme. - In-Seok Kong; Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (IEICE Electron. Express, 2015)

On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR. - Kyung-Sub Son; Jin-Ku Kang (IEICE Electron. Express, 2015)

A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's. - Bum-Hee Choi; Kyung-Sub Son; Jin-Ku Kang (APCCAS, 2016)

A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector. - Nguyen Huu Tho; Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (ISOCC, 2016)

A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's. - Bum-Hee Choi; Kyung-Sub Son; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2016)

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector. - Nguyen Huu Tho; Kyung-Sub Son; Jin-Ku Kang (IEICE Electron. Express, 2017)

A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. - Min Kim; Kyung-Sub Son; Namhoon Kim; Chang Hang Rho; Jin-Ku Kang (ISOCC, 2018)

Design of a third-order delta-sigma TDC with error-feedback structure. - Seong-Mun An; Kyung-Sub Son; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2019)

Eye-open monitor using two-dimensional counter value profile. - Kyung-Sub Son; Yong-Hwan Moon; Sanghun Baek; Namyong Kim; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2019)

A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort. - Yong-Hwan Moon; Jae-Wook Yoo; Young-Soo Ryu; Sang-Ho Kim; Kyung-Sub Son; Jin-Ku Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition. - Kyung-Sub Son; Taek-Joon An; Yong-Hwan Moon; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)