A Novel Solution for Chip-Level Functional Timing Verification. - Rathish Jayabharathi; Kyung Tek Lee; Jacob A. Abraham (VTS, 1997)

Design methodology for a 1.0 GHz microprocessor. - Stephen D. Posluszny; Naoaki Aoki; David Boerstler; Jeffrey L. Burns; Sang H. Dhong; Uttam Ghoshal; H. Peter Hofstee; David P. LaPotin; Kyung T. Lee; David Meltzer; Hung C. Ngo; Kevin J. Nowka; et al. (ICCD, 1998)

Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits. - Kyung Tek Lee; Clay Nordquist; Jacob A. Abraham (VTS, 1998)

A 1.0-GHz single-issue 64-bit powerPC integer processor. - Joel Silberman; Naoaki Aoki; David Boerstler; Jeffrey L. Burns; Sang H. Dhong; Axel Essbaum; Uttam Ghoshal; David F. Heidel; H. Peter Hofstee; Kyung T. Lee; David Meltzer; Hung C. Ngo; et al. (IEEE J. Solid State Circuits, 1998)

Critical path identification and delay tests of dynamic circuits. - Kyung Tek Lee; Jacob A. Abraham (ITC, 1999)

"Timing closure by design, " a high frequency microprocessor design methodology. - Stephen D. Posluszny; Naoaki Aoki; David Boerstler; Paula K. Coulman; Sang H. Dhong; Brian K. Flachs; H. Peter Hofstee; Nobuo Kojima; Ohsang Kwon; Kyung T. Lee; David Meltzer; Kevin J. Nowka; et al. (DAC, 2000)

Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor. - Jason M. Hart; Kyung T. Lee; Dennis Chen; Lik Cheng; Chipai Chou; Anand Dixit; Dale Greenley; Gregory Gruber; Kenneth Ho; Jesse Hsu; Naveen G. Malur; John Wu (IEEE J. Solid State Circuits, 2006)