A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. - Hyun-Woo Lee; Yong-Hoon Kim; Won-Joo Yun; Eun Young Park; Kang Youl Lee; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Kyung Whan Kim; Nam Gyu Rye; Kwan-Weon Kim; Jun Hyun Chun; et al. (ISCAS, 2010)

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. - Hyun-Woo Lee; Hoon Choi; Beom-Ju Shin; Kyung-Hoon Kim; Kyung Whan Kim; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Jae-Hwan Kim; Eun Young Park; Jong-Sam Kim; Jong-Hwan Kim; et al. (IEEE J. Solid State Circuits, 2012)

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Hongjung Kim; Ju Young Kim; Young Jun Park 006; Jae Hwan Kim; Dae Suk Kim; Heat Bit Park; Jin Wook Shin; Jang Hwan Cho; Ki Hun Kwon; et al. (ISSCC, 2014)

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Kang Seol Lee; Sang Jin Byeon; Jin-Hee Cho; Han Ho Jin; Sang Kyun Nam; Jaejin Lee; Jun Hyun Chun; Sung-Joo Hong (VLSIC, 2014)

Design considerations of HBM stacked DRAM and the memory architecture extension. - Dong-Uk Lee; Kang Seol Lee; Yongwoo Lee; Kyung Whan Kim; Jong-Ho Kang; Jaejin Lee; Jun Hyun Chun (CICC, 2015)

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Kang Seol Lee; Sang Jin Byeon; Jae-Hwan Kim; Jin-Hee Cho; Jaejin Lee; Jun Hyun Chun (IEEE J. Solid State Circuits, 2015)

High bandwidth memory(HBM) with TSV technique. - Jong-Chern Lee; Jihwan Kim; Kyung Whan Kim; Young Jun Ku; Dae Suk Kim; Chunseok Jeong; Tae Sik Yun; Hongjung Kim; Ho Sung Cho; Sangmuk Oh; Hyun Sung Lee; Ki Hun Kwon; et al. (ISOCC, 2016)

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. - Jong-Chern Lee; Jihwan Kim; Kyung Whan Kim; Young Jun Ku; Dae Suk Kim; Chunseok Jeong; Tae Sik Yun; Hongjung Kim; Ho Sung Cho; Yeon Ok Kim; Jae-Hwan Kim; Jin Ho Kim; et al. (ISSCC, 2016)

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. - Dongkyun Kim; Minsu Park; Sungchun Jang; Jun-Yong Song; Hankyu Chi; Geunho Choi; Sunmyung Choi; Jaeil Kim; Changhyun Kim; Kyung Whan Kim; Kibong Koo; Seonghwi Song; et al. (ISSCC, 2019)