A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array. - Jung-Sik Kim; Kyung-Woo Nam; Chi Sung Oh; Han Gu Sohn; Donghyuk Lee; Sooyoung Kim; Jong-Wook Park; Yongjun Kim; Mi-Jo Kim; Jin-Guk Kim; Hocheol Lee; Jinhyoung Kwon; et al. (IEEE J. Solid State Circuits, 2008)

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM). - Hyunui Lee; Sukyong Kang; Hye-Seung Yu; Won-Joo Yun; Jae-Hun Jung; Sungoh Ahn; Wang-Soo Kim; Beomyong Kil; Yoo-Chang Sung; Sang-Hoon Shin; Yong-Sik Park; Yong-Hwan Kim; et al. (A-SSCC, 2016)

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (ISSCC, 2016)