Process variation tolerant all-digital multiphase DLL for DDR3 interface. - Heechai Kang; Kyungho Ryu; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (CICC, 2010)

A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface. - Dong-Hoon Jung; Kyungho Ryu; Seong-Ook Jung (IEEE Trans. Consumer Electron., 2010)

A DLL based clock generator for low-power mobile SoCs. - Kyungho Ryu; Dong Hun Jung; Seong-Ook Jung (IEEE Trans. Consumer Electron., 2010)

MTJ based non-volatile flip-flop in deep submicron technology. - Youngdon Jung; Jisu Kim; Kyungho Ryu; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISOCC, 2011)

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (ESSCIRC, 2012)

Integration of dual channel timing formatter system for high speed memory test equipment. - Jaeseok Park; Ingeol Lee; Young-Seok Park; Sung-Geun Kim; Kyungho Ryu; Dong-Hoon Jung; Kangwook Jo; Choong Keun Lee; Hongil Yoon; Seong-Ook Jung; Woo-Young Choi; Sungho Kang 001 (ISOCC, 2012)

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. - Heechai Kang; Kyungho Ryu; Dong-Hoon Jung; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator. - Kyungho Ryu; Dong-Hoon Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). - Jisu Kim; Kyungho Ryu; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop. - Kyungho Ryu; Jisu Kim; Jiwan Jung; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2012)

All-digital 90° phase-shift DLL with a dithering jitter suppression scheme. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Won Lee; Seong-Ook Jung (CICC, 2013)

All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. - Kyungho Ryu; Dong-Hoon Jung; Seong-Ook Jung (ESSCIRC, 2013)

A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management. - Young-Jae An; Kyungho Ryu; Dong-Hoon Jung; Seung-Han Woo; Seong-Ook Jung (ICCE, 2013)

A comparative study of STT-MTJ based non-volatile flip-flops. - Taehui Na; Kyungho Ryu; Jisu Kim; Seung-Hyuk Kang; Seong-Ook Jung (ISCAS, 2013)

ADDLL for Clock-Deskew Buffer in High-Performance SoCs. - Jung-Hyun Park; Dong-Hoon Jung; Kyungho Ryu; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2013)

High-performance low-power magnetic tunnel junction based non-volatile flip-flop. - Taehui Na; Kyungho Ryu; Jisu Kim; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISCAS, 2014)

An MTJ-based non-volatile flip-flop for high-performance SoC. - Youngdon Jung; Jisu Kim; Kyungho Ryu; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (Int. J. Circuit Theory Appl., 2014)

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector. - Kyungho Ryu; Dong-Hoon Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies. - Jisu Kim; Kyungho Ryu; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2014)

All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM. - Dong-Hoon Jung; Young-Jae An; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management. - Young-Jae An; Dong-Hoon Jung; Kyungho Ryu; Seung-Han Woo; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs. - Jung-Hyun Park; Heechai Kang; Dong-Hoon Jung; Kyungho Ryu; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator. - Young-Jae An; Dong-Hoon Jung; Kyungho Ryu; Hyuck-Sang Yim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator. - Kyungho Ryu; Jiwan Jung; Dong-Hoon Jung; Jin Hyuk Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2018)

payGo: Incentive-Comparable Payment Routing Based on Contract Theory. - Kyungho Ryu; Wooseong Kim; Eun-Kyu Lee (IEEE Access, 2020)

An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits. - Kyungho Ryu; Kil-Hoon Lee; Jung-Pil Lim; Jinho Kim; Han Su Pae; Junho Park; Hyun-Wook Lim; Jae-Youl Lee (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Multi-Objective Optimization of Energy Saving and Throughput in Heterogeneous Networks Using Deep Reinforcement Learning. - Kyungho Ryu; Wooseong Kim (Sensors, 2021)

A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond. - Kyungho Ryu; Ji-Yong Jeong; Jung-Pil Lim; Kil-Hoon Lee; Kyongho Kim; Yongil Kwon; Seongjong Yoo; Siwoo Kim; Hyun-Wook Lim; Jae-Youl Lee (ISSCC, 2023)

Energy efficient deployment of aerial base stations for mobile users in multi-hop UAV networks. - Kyungho Ryu; Wooseong Kim (Ad Hoc Networks, 2024)