Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. - Heechun Park; Kyungjoon Chang; Jooyeon Jeong; Jaehoon Ahn; Ki-Seok Chung; Taewhan Kim 001 (ISOCC, 2021)

Analysis of Impacting Multi-stack Standard Cells on Chip Implementation. - Kyungjoon Chang; Taewhan Kim 001 (ISOCC, 2022)

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. - Kyungjoon Chang; Jaehoon Ahn; Heechun Park; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2023)

Pre-route timing prediction and optimization with graph neural network models. - Kyungjoon Chang; Taewhan Kim 001 (Integr., 2024)

DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. - Jaehoon Ahn; Kyungjoon Chang; Kyumyung Choi; Taewhan Kim 001; Heechun Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)