Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC. - Sumin Choi; Heegon Kim; Daniel H. Jung; Jonghoon J. Kim; Jaemin Lim; Hyunsuk Lee; Kyungjun Cho; Joungho Kim; Hyungsoo Kim; Yong-Ju Kim; Yunsaing Kim (3DIC, 2015)

Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module. - Hyunsuk Lee; Kyungjun Cho; Heegon Kim; Sumin Choi; Jaemin Lim; Joungho Kim (3DIC, 2015)

Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC. - Subin Kim; Youngwoo Kim; Kyungjun Cho; Jinwook Song; Joungho Kim (3DIC, 2016)

Miniaturized and high-performance RF packages with ultra-thin glass substrates. - Min Suk Kim; Markondeya Raj Pulugurtha; Youngwoo Kim; Gapyeol Park; Kyungjun Cho; Vanessa Smet; Venky Sundaram; Joungho Kim; Rao R. Tummala (Microelectron. J., 2018)

Low Leakage Electromagnetic Field Level and High Efficiency Using a Novel Hybrid Loop-Array Design for Wireless High Power Transfer System. - Seongsoo Lee; Donghyun Kim 004; Yeonje Cho; Hongseok Kim; Chiuk Song; Seungtaek Jeong; Jinwook Song; Gyeyoung Park; Seokwoo Hong; Junyong Park; Kyungjun Cho; Hyunsuk Lee; et al. (IEEE Trans. Ind. Electron., 2019)

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Jinhyung Lee; Kyungjun Cho; Ji Hwan Park; Junil Moon; Sung-Hak Lee; Tae-Kyun Kim 001; Sanghoon Oh; Seokwoo Choi; Yongsuk Choi; Ho Sung Cho; Tae-Sik Yun; et al. (IEEE J. Solid State Circuits, 2023)

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. - Jinhyung Lee; Kyungjun Cho; Chang Kwon Lee; Yeonho Lee 002; Jae-Hyung Park; Su-Hyun Oh; Yucheon Ju; Chunseok Jeong; Ho Sung Cho; Jaeseung Lee; Tae-Sik Yun; Jin Hee Cho; et al. (ISSCC, 2024)

Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology. - Sungweon Hong; Yunseob Tae; Dongjun Lee; Gijin Park; Jaemyung Lim; Kyungjun Cho; Chunseok Jeong; Myeong-Jae Park; Songnam Hong 001; Jaeduk Han (IEEE Access, 2024)