Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration. - Sung-Yun Lee; Daeyeon Kim; Kyungjun Min; Seokhyeong Kang (ASP-DAC, 2022)

ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks. - Kyungjun Min; Seongbin Kwon; Sung-Yun Lee; Dohun Kim; Sunghye Park; Seokhyeong Kang (ICCAD, 2023)

Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications. - Daeyeon Kim; Sung-Yun Lee; Kyungjun Min; Seokhyeong Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. - Andrew B. Kahng; Seokhyeong Kang; Sayak Kundu; Kyungjun Min; Seonghyeon Park; Bodhisatta Pramanik (DAC, 2024)

CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning. - Sung-Yun Lee; Kyungjun Min; Seokhyeong Kang (DATE, 2024)

Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement. - Jinoh Cho; Jaekyung Im; Jaeseung Lee; Kyungjun Min; Seonghyeon Park; Jaemin Seo; Jongho Yoon 001; Seokhyeong Kang (ASP-DAC, 2025)

Improving LLM-Based Verilog Code Generation with Data Augmentation and RL. - Kyungjun Min; Seonghyeon Park; Hyeonwoo Park; Jinoh Cho; Seokhyeong Kang (DATE, 2025)