A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE. - Kyungmin Baek; Kahyun Kim; Deog-Kyoon Jeong (ISOCC, 2022)

A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. - Daeho Yun; Minsu Park; Kahyun Kim; Kyungmin Baek; Eonhui Lee; Woo-Seok Choi; Deog-Kyoon Jeong (A-SSCC, 2023)

A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. - Kahyun Kim; Daeho Yun; Kyungmin Baek; Woo-Seok Choi; Deog-Kyoon Jeong (ISCAS, 2023)

A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL. - Kyungmin Baek; Jiho Kim; Kahyun Kim; Deog-Kyoon Jeong; Min-Seong Choo (IEEE Trans. Very Large Scale Integr. Syst., 2025)