Coarse-grained reconfigurable architecture for multiple application domains: a case study. - Manhwee Jo; Ganghee Lee; Kyungwook Chang; Kyuseung Han; Kiyoung Choi; Hoonmo Yang; Kiwook Yoon (ICHIT, 2009)

Acceleration of control flow on CGRA using advanced predicated execution. - Kyuseung Han; Jong Kyung Paek; Kiyoung Choi (FPT, 2010)

A host-accelerator communication architecture design for efficient binary acceleration. - Yangsu Kim; Kyuseung Han; Kiyoung Choi (ISOCC, 2011)

State-based full predication for low power coarse-grained reconfigurable architecture. - Kyuseung Han; Seongsik Park; Kiyoung Choi (DATE, 2012)

Compiling control-intensive loops for CGRAs with state-based full predication. - Kyuseung Han; Kiyoung Choi; Jongeun Lee (DATE, 2013)

Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture. - Manhwee Jo; Kyuseung Han; Kiyoung Choi (MUE, 2013)

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. - Kyuseung Han; Junwhan Ahn; Kiyoung Choi (ACM Trans. Archit. Code Optim., 2013)

Leveraging parallelism in the presence of control flow on CGRAs. - Jihyun Ryoo; Kyuseung Han; Kiyoung Choi (ASP-DAC, 2014)

Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. - Manhwee Jo; Dongwook Lee; Kyuseung Han; Kiyoung Choi (Integr., 2014)

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture. - Kyuseung Han; Ganghee Lee; Kiyoung Choi (IEEE Trans. Dependable Secur. Comput., 2014)

TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management. - Woojoo Lee; Kyuseung Han; Yanzhi Wang; Tiansong Cui; Shahin Nazarian; Massoud Pedram (ACM Trans. Design Autom. Electr. Syst., 2017)

TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion. - Kyuseung Han; Jae-Jin Lee; Jinho Lee; Woojoo Lee; Massoud Pedram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform. - Kyuseung Han; Sukho Lee; Jae-Jin Lee; Woojoo Lee; Massoud Pedram (ISLPED, 2019)

Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications. - Hyeonguk Jang; Kyuseung Han; Sukho Lee; Jae-Jin Lee (ISOCC, 2019)

MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems. - Hyeonguk Jang; Kyuseung Han; Sukho Lee; Jae-Jin Lee; Woojoo Lee (IEEE Access, 2019)

A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties. - Kyuseung Han; Jae-Jin Lee; Woojoo Lee; Jinho Lee (IEEE Des. Test, 2019)

TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods. - Woojoo Lee; Taewook Kang; Jae-Jin Lee; Kyuseung Han; Joongheon Kim; Massoud Pedram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

K-means Clustering-specific Lightweight RISC-V processor. - Wooyoung Lee; Jina Park; Changjun Byun; Eunjin Choi; Jae-Hyoung Lee; Woojoo Lee; Kyung Jin Byun; Kyuseung Han (ISOCC, 2021)

Developing a Multicore Platform Utilizing Open RISC-V Cores. - Hyeonguk Jang; Kyuseung Han; Sukho Lee; Jae-Jin Lee; Seung-Yeong Lee; Jae-Hyoung Lee; Woojoo Lee (IEEE Access, 2021)

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes. - Kyuseung Han; Sukho Lee; Kwang-Il Oh; Younghwan Bae; Hyeonguk Jang; Jae-Jin Lee; Woojoo Lee; Massoud Pedram (IEEE Internet Things J., 2021)

Releasing the Memory Bottleneck to Display Video Correctly. - Hyeonguk Jang; Sukho Lee; Jae-Jin Lee; Kyuseung Han (ISOCC, 2022)

Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. - Jina Park; Eunjin Choi; Kyungwon Lee; Jae-Jin Lee; Kyuseung Han; Woojoo Lee (DATE, 2023)

Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. - Jina Park; Kyuseung Han; Eunjin Choi; Sukho Lee; Jae-Jin Lee; Woojoo Lee; Massoud Pedram (ISLPED, 2023)

Optimizing Implementation of SNN for Embedded System. - Hyeonguk Jang; Jae-Jin Lee; Kyuseung Han (ICACT, 2024)

STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs. - Kyuseung Han; Hyunseok Kwak; Kwang-Il Oh; Sukho Lee; Hyeonguk Jang; Jae-Jin Lee; Woojoo Lee (ISLPED, 2024)

Day-Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection. - Eunjin Choi; Jina Park; Kyeongwon Lee; Jae-Jin Lee; Kyuseung Han; Woojoo Lee (J. Syst. Archit., 2024)

Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes. - Jina Park; Kyuseung Han; Eunjin Choi; Jae-Jin Lee; Kyeongwon Lee; Woojoo Lee; Massoud Pedram (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)