Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey. - W. Deweerd; Vidya Kaushik; J. Chen; Y. Shimamoto; Tom Schram; L.-Å. Ragnarsson; Annelies Delabie; Luigi Pantisano; B. Eyckens; J. W. Maes (Microelectron. Reliab., 2005)

Modelling mobility degradation due to remote Coulomb scattering from dielectric charges and its impact on MOS device performance. - G. S. Lujan; Wim Magnus; L.-Å. Ragnarsson; Stefan Kubicek; Stefan De Gendt; Marc M. Heyns; Kristin De Meyer (Microelectron. Reliab., 2005)

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors. - Tom Schram; L.-Å. Ragnarsson; G. S. Lujan; W. Deweerd; J. Chen; W. Tsai; K. Henson; R. J. P. Lander; J. C. Hooker; J. Vertommen (Microelectron. Reliab., 2005)

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? - Thomas Chiarella; Liesbeth Witters; Abdelkarim Mercha; Christoph Kerner; Rok Dittrich; Michal Rakowski; Claude Ortolland; Lars-Åke Ragnarsson; Bertrand Parvais; An De Keersgieter; Stefan Kubicek; Augusto Redolfi; et al. (ESSCIRC, 2009)

Reliability of thin ZrO2 gate dielectric layers. - Robert O'Connor; Greg Hughes; Thomas Kauerauf; Lars-Åke Ragnarsson (Microelectron. Reliab., 2011)

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. - Jacopo Franco; Ben Kaczer; Jérôme Mitard; Maria Toledano-Luque; Felice Crupi; Geert Eneman; Ph. J. Rousse; Tibor Grasser; M. Cho; Thomas Kauerauf; Liesbeth Witters; Geert Hellings; et al. (ICICDT, 2012)

BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic. - Jacopo Franco; S. Graziano; Ben Kaczer; Felice Crupi; Lars-Åke Ragnarsson; Tibor Grasser; Guido Groeseneken (Microelectron. Reliab., 2012)

Silicon LEDs in FinFET technology. - Giulia Piccolo; Piet I. Kuindersma; Lars-Åke Ragnarsson; Raymond J. E. Hueting; Nadine Collaert; Jurriaan Schmitz (ESSDERC, 2014)

Modeling FinFET metal gate stack resistance for 14nm node and beyond. - Kenichi Miyaguchi; Bertrand Parvais; Lars-Åke Ragnarsson; Piet Wambacq; Praveen Raghavan; Abdelkarim Mercha; Anda Mocuta; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper. - Jacopo Franco; Hiroaki Arimura; J.-F. de Marneffe; A. Vandooren; L.-Å. Ragnarsson; Zhicheng Wu; Dieter Claes; E. Dentoni Litta; N. Horiguchi; Kris Croes; Dimitri Linten; Tibor Grasser; et al. (ICICDT, 2021)

A comprehensive variability study of doped HfO2 FeFET for memory applications. - Nicolo Ronchi; Lars-Åke Ragnarsson; Umberto Celano; Ben Kaczer; K. Kaczmarek; K. Banerjee; Sean R. C. McMitchell; Geert Van den Bosch; Jan Van Houdt (IMW, 2022)

Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET. - Hiroaki Arimura; S. Brus; Jacopo Franco; Yusuke Oniki; A. Vandooren; T. Conard; B. T. Chan; B. Kannan; M. Samiee; W. Li; P. Deminskyi; E. Shero; et al. (VLSI Technology and Circuits, 2023)

Transition-state-theory-based interpretation of Landau double well potential for ferroelectrics. - Md Nur K. Alam; Sergiu Clima; Ben Kaczer; Philippe Roussel; Brecht Truijen; Lars-Åke Ragnarsson; N. Horiguchi; Marc M. Heyns; Jan Van Houdt (CoRR, 2024)

Energon: A Sustainability-Driven Modeling Framework for AI Data Centers. - Wenzhe Guo; Joyjit Kundu; Uras Tos; Giuliano Sisto; Cedric Rolin; Lars-Åke Ragnarsson; Timon Evenblij (ISPASS, 2025)