A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation. - Laimin Du; Leibin Ni; Xiong Liu; Wei Mao 002; Hao Yu 001 (APCCAS, 2022)

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Wei Mao 002; Junzhuo Zhou; Boyu Li; Zhengke Yang; Shuxing Yang; Laimin Du; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks. - Wei Mao 002; Liuyao Dai; Kai Li 024; Quan Cheng; Yuhang Wang; Laimin Du; Shaobo Luo; Mingqiang Huang; Hao Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier. - Laimin Du; Leibin Ni; Xiong Liu; Guanqi Peng; Kai Li 024; Wei Mao 002; Hao Yu 001 (IEEE Open J. Circuits Syst., 2024)