Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. - Irith Pomeranz; Sudhakar M. Reddy; Lakshmi N. Reddy (ICCAD, 1991)

COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (ITC, 1991)

SPADES: a simulator for path delay faults in sequential circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (EURO-DAC, 1992)

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. - Lakshmi N. Reddy; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1992)

A Small Test Generator for Large Designs. - Sandip Kundu; Leendert M. Huisman; Indira Nair; Vijay S. Iyengar; Lakshmi N. Reddy (ITC, 1992)

COMPACTEST: a method to generate compact test sets for combinational circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

BooleDozer: Logic synthesis for ASICs. - Leon Stok; David S. Kung 001; Daniel Brand; Anthony D. Drumm; Andrew J. Sullivan; Lakshmi N. Reddy; Nathaniel Hieter; David J. Geiger; Han Hsun Chao; Peter J. Osler (IBM J. Res. Dev., 1996)

Performance Driven Optimization of Network Length in Physical Placement. - Wilm E. Donath; Prabhakar Kudva; Lakshmi N. Reddy (ICCD, 1999)

Transformational Placement and Synthesis. - Wilm E. Donath; Prabhakar Kudva; Leon Stok; Paul Villarrubia; Lakshmi N. Reddy; Andrew Sullivan; Kanad Chakraborty (DATE, 2000)

An Integrated Environment for Technology Closure of Deep-Submicron IC Designs. - Louise Trevillyan; David S. Kung 001; Ruchir Puri; Lakshmi N. Reddy; Michael A. Kazda (IEEE Des. Test Comput., 2004)

Placement-Driven Synthesis Design Closure Tool. - Charles J. Alpert; Nathaniel Hieter; Arjen Mets; Ruchir Puri; Lakshmi N. Reddy; Haoxing Ren; Louise Trevillyan (Handbook of Algorithms for Physical Design Automation, 2008)

Logical and physical restructuring of fan-in trees. - Hua Xiang 001; Haoxing Ren; Louise Trevillyan; Lakshmi N. Reddy; Ruchir Puri; Minsik Cho (ISPD, 2010)

Design methodology for the IBM POWER7 microprocessor. - Joshua Friedrich; Ruchir Puri; Uwe Brandt; Markus Bühler; Jack DiLullo; Jeremy Hopkins; Mozammel Hossain; Michael A. Kazda; Joachim Keinert; Zahi M. Kurzum; Douglass Lamb; Alice Lee; et al. (IBM J. Res. Dev., 2011)

GLARE: global and local wiring aware routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (DAC, 2012)

Intuitive ECO synthesis for high performance circuits. - Haoxing Ren; Ruchir Puri; Lakshmi N. Reddy; Smita Krishnaswamy; Cindy Washburn; Joel Earl; Joachim Keinert (DATE, 2013)

Depth controlled symmetric function fanin tree restructure. - Hua Xiang 001; Lakshmi N. Reddy; Louise Trevillyan; Ruchir Puri (ICCAD, 2013)

Techniques for scalable and effective routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2014)

OWARU: free space-aware timing-driven incremental placement. - Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin (ICCAD, 2016)

Gate movement for timing improvement on row based Dual-VDD designs. - Hua Xiang 001; Lakshmi N. Reddy; Haifeng Qian; Ching Zhou; Yu-Shiang Lin; Fanchieh Yee; Andrew Sullivan; Pong-Fei Lu (ISQED, 2016)

Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis. - Mohd Anwar; Sourav Saha; Matthew M. Ziegler; Lakshmi N. Reddy (VLSID, 2016)

Interconnect Optimization Considering Multiple Critical Paths. - Jiang Hu; Ying Zhou; Yaoguang Wei; Stephen T. Quay; Lakshmi N. Reddy; Gustavo E. Téllez; Gi-Joon Nam (ISPD, 2018)

OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. - Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. - Rongjian Liang; Hua Xiang 001; Diwesh Pandey; Lakshmi N. Reddy; Shyam Ramji; Gi-Joon Nam; Jiang Hu (ISPD, 2020)

FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. - Rongjian Liang; Jinwook Jung; Hua Xiang 001; Lakshmi N. Reddy; Alexey Lvov; Jiang Hu; Gi-Joon Nam (ICCAD, 2021)

Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning. - Matthew M. Ziegler; Lakshmi N. Reddy; Robert L. Franch (ISPD, 2022)

Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. - Rongjian Liang; Hua Xiang 001; Diwesh Pandey; Lakshmi N. Reddy; Shyam Ramji; Gi-Joon Nam; Jiang Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)