A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology. - Chihun Lee; Lan-chou Cho; Shen-Iuan Liu (CICC, 2006)

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS. - Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu (ISSCC, 2007)

A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology. - Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2007)

3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology. - Kun-Hung Tsai; Lan-Chou Cho; Jia-Hao Wu; Shen-Iuan Liu (ISSCC, 2008)

A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS. - Chihun Lee; Lan-Chou Cho; Jia-Hao Wu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. - Lan-Chou Cho; Chihun Lee; Chao-Ching Hung; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2009)

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. - Lan-Chou Cho; Hsiang-Hui Chang; Augusto Marques; Albert Yang; Chinq-Shiun Chiu; Guang-Kaai Dehng (A-SSCC, 2011)

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC. - Ivan Siu-Chuang Lu; Chi-Yao Yu; Yen-Horng Chen; Lan-chou Cho; Chih-hao Eric Sun; Chih-Chun Tang; George Chien (ISSCC, 2011)

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. - Chi-Yao Yu; Ivan Siu-Chuang Lu; Yen-Horng Chen; Lan-chou Cho; Chih-hao Eric Sun; Chih-Chun Tang; Hsiang-Hui Chang; Wen-Chang Lee; Sheng-Jui Huang; Tzung-Han Wu; Chinq-Shiun Chiu; George Chien (IEEE J. Solid State Circuits, 2011)

A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. - Jie-Wei Lai; Chi-Hsueh Wang; Kaipon Kao; Anson Lin; Yi-Hsien Cho; Lan-chou Cho; Meng-Hsiung Hung; Xin-Yu Shih; Che-Min Lin; Sheng-Hong Yan; Yuan-Hung Chung; Paul C. P. Liang; et al. (ISSCC, 2013)

28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and. - YuLi Hsueh; Lan-Chou Cho; Chih-Hsien Shen; Yi-Chien Tsai; Tzu-Chan Chueh; Tao-Yao Chang; Jui-Lin Hsu; Jing-Hong Conan Zhan (ISSCC, 2014)

A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. - Feng-Wei Kuo; Masoud Babaie; Huan-Neng Ron Chen; Kyle Yen; Jinn-Yeh Chien; Lanchou Cho; Fred Kuo; Chewnpu Jou; Fu-Lung Hsueh; Robert Bogdan Staszewski (ESSCIRC, 2015)

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. - Feng-Wei Kuo; Sandro Binsfeld Ferreira; Masoud Babaie; Huan-Neng Ron Chen; Lan-chou Cho; Chewnpu Jou; Fu-Lung Hsueh; Guanzhong Huang; Iman Madadi; Massoud Tohidian; Robert Bogdan Staszewski (VLSI Circuits, 2016)

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. - Masoud Babaie; Feng-Wei Kuo; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Fu-Lung Hsueh; Mina Shahmohammadi; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2016)

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. - Feng-Wei Kuo; Sandro Binsfeld Ferreira; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Fu-Lung Hsueh; Iman Madadi; Massoud Tohidian; Mina Shahmohammadi; Masoud Babaie; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2017)

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. - Feng-Wei Kuo; Masoud Babaie; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Mark Chen 001; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. - Feng-Wei Kuo; Zhirui Zong; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Mark Chen 001; Robert Bogdan Staszewski (ESSCIRC, 2019)

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation. - Kai Xu; Feng-Wei Kuo; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Mark Chen 001; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2019)

A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. - Chua-Chin Wang; Shih-Heng Luo; Hsin-Che Wu; Ralph Gerard B. Sangalang; Chewnpu Jou; Harry Hsia; Lan-Chou Cho (AICAS, 2024)

A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage. - Chua-Chin Wang; Shih-Heng Luo; Hsin-Che Wu; Ralph Gerard B. Sangalang; Chewnpu Jou; Harry Hsia; Lan-Chou Cho (IEEE Access, 2025)