Enriching C-based High-Level Synthesis with parallel pattern templates. - Lana Josipovic; Nithin George; Paolo Ienne (FPT, 2016)

From C to elastic circuits. - Lana Josipovic; Philip Brisk; Paolo Ienne (ACSSC, 2017)

An Out-of-Order Load-Store Queue for Spatial Computing. - Lana Josipovic; Philip Brisk; Paolo Ienne (ACM Trans. Embed. Comput. Syst., 2017)

Dynamically Scheduled High-level Synthesis. - Lana Josipovic; Radhika Ghosal; Paolo Ienne (FPGA, 2018)

Speculative Dataflow Circuits. - Lana Josipovic; Andrea Guerrieri; Paolo Ienne (FPGA, 2019)

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. - Lana Josipovic; Atri Bhattacharyya; Andrea Guerrieri; Paolo Ienne (FPT, 2019)

Combining Dynamic & Static Scheduling in High-level Synthesis. - Jianyi Cheng; Lana Josipovic; George A. Constantinides; Paolo Ienne; John Wickerson (FPGA, 2020)

Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. - Lana Josipovic; Andrea Guerrieri; Paolo Ienne (FPGA, 2020)

High-Level Synthesis of Dynamically Scheduled Circuits. - Lana Josipovic (2021)

Dynamic Inter-Block Scheduling for HLS. - Jianyi Cheng; Lana Josipovic; George A. Constantinides; John Wickerson (FPL, 2022)

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. - Ayatallah Elakhras; Andrea Guerrieri; Lana Josipovic; Paolo Ienne (FPL, 2022)

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. - Carmine Rizzi; Andrea Guerrieri; Paolo Ienne; Lana Josipovic (FPL, 2022)

Load-Store Queue Sizing for Efficient Dataflow Circuits. - Jiantao Liu; Carmine Rizzi; Lana Josipovic (FPT, 2022)

29th Reconfigurable Architectures Workshop (RAW 2022). - Jürgen Becker 001; Lana Josipovic; Viktor K. Prasanna; Marco D. Santambrogio; Ramachandran Vaidyanathan (IPDPS Workshops, 2022)

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. - Jianyi Cheng; Lana Josipovic; George A. Constantinides; Paolo Ienne; John Wickerson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

From C/C++ Code to High-Performance Dataflow Circuits. - Lana Josipovic; Andrea Guerrieri; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Buffer Placement and Sizing for High-Performance Dataflow Circuits. - Lana Josipovic; Shabnam Sheikhha; Andrea Guerrieri; Paolo Ienne; Jordi Cortadella (ACM Trans. Reconfigurable Technol. Syst., 2022)

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits. - Carmine Rizzi; Andrea Guerrieri; Lana Josipovic (DAC, 2023)

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. - Ayatallah Elakhras; Riya Sawhney; Andrea Guerrieri; Lana Josipovic; Paolo Ienne (FPGA, 2023)

Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. - Jiahui Xu; Emmet Murphy; Jordi Cortadella; Lana Josipovic (FPGA, 2023)

MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. - Hanyu Wang; Carmine Rizzi; Lana Josipovic (ICCAD, 2023)

Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. - Jiahui Xu; Lana Josipovic (ICCAD, 2023)

Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. - Jianyi Cheng; Lana Josipovic; John Wickerson; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2023)

Resource Sharing in Dataflow Circuits. - Lana Josipovic; Axel Marmet; Andrea Guerrieri; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2023)

FPGA EDA - Design Principles and Implementation - Kaihui Tu; Xifan Tang; Cunxi Yu; Lana Josipovic; Zhufei Chu (Springer, 2024)

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. - Ayatallah Elakhras; Andrea Guerrieri; Lana Josipovic; Paolo Ienne (FPGA, 2024)

DynaRapid: From C to FPGA in a Few Seconds. - Andrea Guerrieri; Srijeet Guha; Lana Josipovic; Paolo Ienne (FPGA, 2024)

Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. - Jiahui Xu; Lana Josipovic (FPGA, 2024)

DynaRapid: Fast-Tracking from C to Routed Circuits. - Andrea Guerrieri; Srijeet Guha; Chris Lavin; Eddie Hung; Lana Josipovic; Paolo Ienne (FPL, 2024)

Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits. - Jiantao Liu; Maksymilian Graczyk; Andrea Guerrieri; Lana Josipovic (FPL, 2024)

Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNs. - Emmet Murphy; Lana Josipovic (ICCAD, 2024)

ElasticMiter: Formally Verified Dataflow Circuit Rewrites. - Ayatallah Elakhras; Jiahui Xu; Martin Erhart; Paolo Ienne; Lana Josipovic (ASPLOS (2), 2025)

CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS. - Jiahui Xu; Lana Josipovic (ASPLOS (1), 2025)

SimGen: Simulation Pattern Generation for Efficient Equivalence Checking. - Carmine Rizzi; Sarah Brunner; Alan Mishchenko; Lana Josipovic (DATE, 2025)

DRSA: Accelerating Macro Placement on Commercial FPGAs. - Menzo Bouaissi; Paolo Ienne; Lana Josipovic; Andrea Guerrieri (FCCM, 2025)

Resource and Phase Awareness for Dynamically Scheduled High-Level Synthesis. - Mathias Bouilloud; Lana Josipovic; Wayne Luk (HEART, 2025)

OptiPIM: Optimizing Processing-in-Memory Acceleration Using Integer Linear Programming. - Jiantao Liu; Minxuan Zhou; Yue Pan; Chien-Yi Yang; Lana Josipovic; Tajana Rosing (ISCA, 2025)