Making split fabrication synergistically secure and manufacturable. - Lang Feng 001; Yujie Wang; Jiang Hu; Wai-Kei Mak; Jeyavijayan Rajendran (ICCAD, 2017)

Exploring Serverless Computing for Neural Network Training. - Lang Feng 001; Prabhakar Kudva; Dilma Da Silva; Jiang Hu (IEEE CLOUD, 2018)

Layout recognition attacks on split manufacturing. - Wenbin Xu; Lang Feng 001; Jeyavijayan Rajendran; Jiang Hu (ASP-DAC, 2019)

How Much Does Regularity Help FPGA Placement? - Hongxin Kong; Lang Feng 001; Chunhua Deng; Bo Yuan 001; Jiang Hu (FPT, 2020)

FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation. - Lang Feng 001; Jeff Huang 001; Jiang Hu; Abhijith Reddy (ACM Trans. Design Autom. Electr. Syst., 2021)

RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity. - Lang Feng 001; Jiayi Huang 001; Luyi Li; Haochen Zhang; Zhongfeng Wang 001 (IEEE Trans. Computers, 2022)

Toward Taming the Overhead Monster for Data-flow Integrity. - Lang Feng 001; Jiayi Huang 001; Jeff Huang 001; Jiang Hu (ACM Trans. Design Autom. Electr. Syst., 2022)

GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design. - Lang Feng 001; Wenjian Liu; Chuliang Guo; Ke Tang; Cheng Zhuo; Zhongfeng Wang 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving. - Lang Feng 001; Jin Sha; Zhongfeng Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

ProMiSE: A High-Performance Programmable Hardware Monitor for High Security Enforcement of Software Execution. - Xinrui Wang; Lang Feng 001; Zhongfeng Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Hardware-Assisted Control-Flow Integrity Enhancement for IoT Devices. - Weiyi Wang; Lang Feng 001; Zhiguo Shi 001; Cheng Zhuo; Jiming Chen 001 (DATE, 2024)

A Rule-Based High Efficient Obstacle-Avoiding RSMT Algorithm for VLSI Routing. - Junhao Guo; Hongxin Kong; Lang Feng 001 (ISCAS, 2024)

A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA. - Jing Tian 004; Bo Wu; Lang Feng 001; Haochen Zhang; Zhongfeng Wang 001 (IACR Cryptol. ePrint Arch., 2024)

RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices. - Yuxing Chen; Xinrui Wang; Suwen Song; Lang Feng 001; Zhongfeng Wang 001 (IEEE Trans. Computers, 2024)

Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins. - Ke Tang; Lang Feng 001; Zhongfeng Wang 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender. - Luyi Li; Jiayi Huang 001; Lang Feng 001; Zhongfeng Wang 001 (IEEE Trans. Computers, 2024)

An MIP-based Force-directed Large Scale Placement Refinement Algorithm. - Zewen Li; Ke Tang; Lang Feng 001; Zhongfeng Wang 001 (ASP-DAC, 2025)

Hybrid Exact and Heuristic Efficient Transistor Network Optimization for Multi-Output Logic. - Lang Feng 001; Rongjian Liang; Hongxin Kong (DATE, 2025)

CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC. - Xihao Liang; Yujie Wang; Xupengkai Lu; Lang Feng 001; Jixiang Zhu; Ying Wang 001; Yinhe Han 001 (ISCAS, 2025)

A High Efficient and Scalable Obstacle-Avoiding VLSI Global Routing Flow. - Junhao Guo; Hongxin Kong; Lang Feng 001 (CoRR, 2025)

PreSIT: Predict Cryptography Computations in SGX-Style Integrity Trees. - Xinrui Wang; Lang Feng 001; Zhongfeng Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline. - Yuefei Wang; Wendong Mao; Lang Feng 001; Jin Sha; Zhongfeng Wang 001 (ACM Trans. Design Autom. Electr. Syst., 2025)