Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Zhigang Jiang; Lang Tan; Yu Zhang; Yu Hu 001; Wen-Ben Jone; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Lizhen Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Recurrence, Analysis and Prototype Regression Verification of Occasional Problems in Chip Design. - Zhenhai Ning; Dejian Li; Xi Feng; Yanxin Zhang; Longlong He; Jinwang Li; Lang Tan; Lixin Yang 007 (EITCE, 2022)

Implementation and Debugging Method of a High-end Controller Chip Safety Debugging System. - Yanxin Zhang; Longlong He; Zhenhai Ning; Jinwang Li; Lang Tan; Lixin Yang 007 (EITCE, 2022)

Boot process of RISC-V multi-core heterogeneous SoC integrated with eFPGA. - Po Gao; Yanxin Zhang; Lang Tan; Lixin Yang 007; Bin Niu; Shengli Yan; Dejian Li; Zhihua Wang 001 (EITCE, 2024)