VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash. - Lanlan Cui; Fei Wu 005; Xiaojian Liu; Meng Zhang 014; Changsheng Xie (ICCD, 2019)

BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory. - Meng Zhang 014; Fei Wu 005; Qin Yu; Weihua Liu; Lanlan Cui; Yahui Zhao; Changsheng Xie (DATE, 2020)

A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash. - Lanlan Cui; Xiaojian Liu; Fei Wu 005; Zhonghai Lu; Changsheng Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision. - Lanlan Cui; Fei Wu 005; Xiaojian Liu; Meng Zhang 014; Renzhi Xiao; Changsheng Xie (ACM Trans. Design Autom. Electr. Syst., 2022)

Learning-Based Collaborative Service Placement for AI-oriented Mobile Edge Computing. - Wei Li; Miao Li; Yuezhao Liu; Jiong Liu; Lanlan Cui (CBD, 2023)

LVLDPC: Intra-Layer Variation Aware LDPC Coding for 3D TLC NAND Flash Memory. - Lanlan Cui; Meng Zhang 014; Fei Wu 005 (ICCD, 2024)

Read-Optimized Persistent Hash Index for Query Acceleration through Fingerprint Filtering and Lock-Free Prefetching. - Renzhi Xiao; Dan Feng 001; Yuchong Hu; Hong Jiang 001; Lin Wang; Yucheng Zhang; Lanlan Cui; Guanglei Xu; Fang Wang 001 (ICCD, 2024)

A Novel Auralization Model for Network Security Situation Assessment. - Yeqiu Xiao; Yibin Ma; Yichuan Wang; Kun Jiang 001; Lanlan Cui (NaNA, 2024)

DHD: Double Hard Decision Decoding Scheme for NAND Flash Memory. - Lanlan Cui; Yichuan Wang 003; Renzhi Xiao; Miao Li; Xiaoxue Liu; Xinhong Hei 001 (DATE, 2025)

Write-Optimized Persistent Hash Index for Non-Volatile Memory. - Renzhi Xiao; Dan Feng 001; Yuchong Hu; Yucheng Zhang; Lanlan Cui; Lin Wang (DATE, 2025)