Timing Verification on a 1.2M-Device Full-Custom CMOS Design. - Jengwei Pan; Larry L. Biro; Joel Grodstein; William J. Grundmann; Yao-Tsung Yen (DAC, 1991)

The NVAX and NVAX+ High-Performance VAX Microprocessor. - G. Michael Uhler; Debra Bernstein; Larry L. Biro; John F. Brown III; John H. Edmondson; Jeffrey D. Pickholtz; Rebecca L. Stamm (Digit. Tech. J., 1992)

A 100-MHz macropipelined VAX microprocessor. - Roy W. Badeau; R. Iris Bahar; Debra Bemstein; Larry L. Biro; William J. Bowhill; John F. Brown III; Michael A. Case; Ruben W. Castelino; Elizabeth M. Cooper; Maureen A. Delaney; David R. Deverell; John H. Edmondson; et al. (IEEE J. Solid State Circuits, 1992)

Power Considerations in the Design of the Alpha 21264 Microprocessor. - Michael K. Gowan; Larry L. Biro; Daniel B. Jackson (DAC, 1998)

Circuit implementation of a 600 MHz superscalar RISC microprocessor. - Mark Matson; Dan Bailey; Shane L. Bell; Larry L. Biro; Steve Butler; John Clouser; Jim Farrell; Mike Gowan; Donald A. Priore; Kathryn Wilcox (ICCD, 1998)

A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor. - Cheolmin Park; Roy W. Badeau; Larry L. Biro; Jonathan Chang; Tejpal Singh; Jim Vash; Bo Wang; Tom Wang (ISSCC, 2010)

A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. - Reid J. Riedlinger; Rohit Bhatia; Larry L. Biro; William J. Bowhill; Eric S. Fetzer; Paul E. Gronowski; Tom Grutkowski (ISSCC, 2011)

A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. - Reid J. Riedlinger; Ron Arnold; Larry L. Biro; William J. Bowhill; Jason Crop; Kevin Duda; Eric S. Fetzer; Olivier Franza; Tom Grutkowski; Casey Little; Charles Morganti; Gary Moyer; et al. (IEEE J. Solid State Circuits, 2012)