A Notation for Describing Multiple Views of VLSI Circuits. - Jean-Loup Baer; Meei-Chiueh Liem; Larry McMurchie; Rudolf Nottrott; Lawrence Snyder 001; Wayne Winder (DAC, 1988)

Apex: two architectures for generating parametric curves and surfaces. - Tony DeRose; Mary L. Bailey; Bill Barnard; Robert Cypher; David Dobrikin; Carl Ebeling; Smaragda Konstantinidou; Larry McMurchie; Haim Mizrahi; Bill Yost (Vis. Comput., 1989)

Hybrid compiled/interpreted simulation of MOS circuits. - Larry McMurchie; Craig Anderson 001; Gaetano Borriello (EURO-DAC, 1991)

PathFinder: A Negotiation-based Performance-driven Router for FPGAs. - Larry McMurchie; Carl Ebeling (FPGA, 1995)

Placement and routing tools for the Triptych FPGA. - Carl Ebeling; Larry McMurchie; Scott Hauck; Steven M. Burns (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Emerald: An Architecture-Driven Tool Compiler for FPGAs. - Darren C. Cronquist; Larry McMurchie (FPGA, 1996)

Output Prediction Logic: A High-Performance CMOS Design Technique. - Larry McMurchie; Su Kio; Gin Yee; Tyler Thorp; Carl Sechen (ICCD, 2000)

Distributed-memory parallel routing for field-programmable gatearrays. - Pak K. Chan; Martine D. F. Schlag; Carl Ebeling; Larry McMurchie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A High-Performance 64-bit Adder Implemented in Output Prediction Logic. - Sheng Sun; Larry McMurchie; Carl Sechen (ARVLSI, 2001)

WTA: waveform-based timing analysis for deep submicron circuits. - Larry McMurchie; Carl Sechen (ICCAD, 2002)

A high performance CMOS programmable logic core. - Yi Han; Larry McMurchie; Carl Sechen (CICC, 2004)

409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. - Sheng Sun; Yi Han; Xinyu Guo; Kian Haur Chong; Larry McMurchie; Carl Sechen (ISVLSI, 2005)

A 64b adder using self-calibrating differential output prediction logic. - Kian Haur Chong; Larry McMurchie; Carl Sechen (ISSCC, 2006)