Optimal usage of CMOS within a BiCMOS technology. - Larry Wissel; Elliot L. Gould (IEEE J. Solid State Circuits, 1992)

Device and circuit design issues in SOI technology. - Ghavam G. Shahidi; Atul Ajmera; Fariborz Assaderaghi; Ronald J. Bolam; Harold Hovel; Effendi Leobandung; Werner Rausch; Devendra Sadana; Dominic Schepis; Lawrence F. Wagner; Larry Wissel; Kun Wu; et al. (CICC, 1999)

Behavioral modeling for timing, noise, and signal integrity analysis. - Jerry D. Hayes; Larry Wissel (CICC, 2001)

Managing soft errors in ASICs. - Larry Wissel; Scott Pheasant; Rory Loughran; Chris LeBlanc; Bill Klaasen (CICC, 2002)

Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited). - David A. Sunderland; Gary L. Duncan; Brad J. Rasmussen; Harry E. Nichols; Daniel T. Kain; Lawrence C. Lee 002; Brian A. Clebowicz; Richard W. Hollis IV; Larry Wissel; Tad Wilder (ISQED, 2002)

Estimation of Iddq for early chip and technology design decisions. - Terence Hook; Larry Wissel; David Mazgaj (CICC, 2003)

Modeling leakage in ASIC libraries. - Susan Lichtensteiger; Larry Wissel; Jim Engel; Paul Sulva (CICC, 2005)

Poster session. - Larry Wissel (CICC, 2005)

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology. - Larry Wissel; Harold Pilo; Chris LeBlanc; Xiaopeng Wang; Steve Lamphier; Michael Fragano (CICC, 2007)

Circuit design and modeling for soft errors. - A. J. KleinOsowski; Ethan H. Cannon; Phil Oldiges; Larry Wissel (IBM J. Res. Dev., 2008)