RISPP: Rotating Instruction Set Processing Platform. - Lars Bauer; Muhammad Shafique 001; Simon Kramer 002; Jörg Henkel (DAC, 2007)

An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (ESTIMedia, 2007)

A Self-Adaptive Extensible Embedded Processor. - Lars Bauer; Muhammad Shafique 001; Dirk Teufel; Jörg Henkel (SASO, 2007)

Run-time instruction set selection in a transmutable embedded processor. - Lars Bauer; Muhammad Shafique 001; Jörg Henkel (DAC, 2008)

Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set. - Lars Bauer; Muhammad Shafique 001; Stephanie Kreutz; Jörg Henkel (DATE, 2008)

A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. - Lars Bauer; Muhammad Shafique 001; Jörg Henkel (FPL, 2008)

3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (ISLPED, 2008)

Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. - Lars Bauer; Muhammad Shafique 001; Jörg Henkel (IEEE Trans. Very Large Scale Integr. Syst., 2008)

MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. - Lars Bauer; Muhammad Shafique 001; Jörg Henkel (CODES+ISSS, 2009)

Cross-architectural design space exploration tool for reconfigurable processors. - Lars Bauer; Muhammad Shafique 001; Jörg Henkel (DATE, 2009)

A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (DATE, 2009)

RISPP: A run-time adaptive reconfigurable embedded processor. - Lars Bauer; Muhammad Shafique 001; Jörg Henkel (FPL, 2009)

REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (ICCAD, 2009)

RISPP: a run-time adaptive reconfigurable embedded processor. - Lars Bauer (2009)

KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. - Ralf König 001; Lars Bauer; Timo Stripf; Muhammad Shafique 001; Waheed Ahmed; Jürgen Becker 001; Jörg Henkel (DATE, 2010)

enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (DATE, 2010)

Selective instruction set muting for energy-aware adaptive processors. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (ICCAD, 2010)

Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (J. Signal Process. Syst., 2010)

Run-time Adaptation for Reconfigurable Embedded Processors. - Lars Bauer; Jörg Henkel (Springer, 2011)

Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors. - Lars Bauer; Muhammad Shafique 001; Jörg Henkel (AHS, 2011)

Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors. - Waheed Ahmed; Muhammad Shafique 001; Lars Bauer; Jörg Henkel (CODES+ISSS, 2011)

Design and architectures for dependable embedded systems. - Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann 001; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; et al. (CODES+ISSS, 2011)

DistRM: distributed resource management for on-chip many-core systems. - Sebastian Kobbe; Lars Bauer; Daniel Lohmann; Wolfgang Schröder-Preikschat; Jörg Henkel (CODES+ISSS, 2011)

mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions. - Waheed Ahmed; Muhammad Shafique 001; Lars Bauer; Jörg Henkel (DATE, 2011)

Minority-Game-based resource allocation for run-time reconfigurable multi-core processors. - Muhammad Shafique 001; Lars Bauer; Waheed Ahmed; Jörg Henkel (DATE, 2011)

Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors. - Waheed Ahmed; Muhammad Shafique 001; Lars Bauer; Manuel Hammerich; Jörg Henkel; Jürgen Becker 001 (FCCM, 2011)

OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware". - Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang 004; Hans-Joachim Wunderlich; Jörg Henkel (AHS, 2012)

Invasive manycore architectures. - Jörg Henkel; Andreas Herkersdorf; Lars Bauer; Thomas Wild; Michael Hübner 001; Ravi Kumar Pujari; Artjom Grudnitsky; Jan Heisswolf; Aurang Zaib; Benjamin Vogel; Vahid Lari; Sebastian Kobbe (ASP-DAC, 2012)

Partial online-synthesis for mixed-grained reconfigurable architectures. - Artjom Grudnitsky; Lars Bauer; Jörg Henkel (DATE, 2012)

Dynamic cache management in multi-core architectures through run-time adaptation. - Fazal Hameed; Lars Bauer; Jörg Henkel (DATE, 2012)

PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors. - Lars Bauer; Artjom Grudnitsky; Muhammad Shafique 001; Jörg Henkel (FCCM, 2012)

Transparent structural online test for reconfigurable systems. - Mohamed Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang 004; Jörg Henkel; Hans-Joachim Wunderlich (IOLTS, 2012)

Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies. - Fazal Hameed; Lars Bauer; Jörg Henkel (CASES, 2013)

Hardware acceleration for programs in SSA form. - Manuel Mohr; Artjom Grudnitsky; Tobias Modschiedler; Lars Bauer; Sebastian Hack; Jörg Henkel (CASES, 2013)

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache. - Fazal Hameed; Lars Bauer; Jörg Henkel (CODES+ISSS, 2013)

Reliable on-chip systems in the nano-era: lessons learnt and future trends. - Jörg Henkel; Lars Bauer; Nikil D. Dutt; Puneet Gupta 001; Sani R. Nassif; Muhammad Shafique 001; Mehdi Baradaran Tahoori; Norbert Wehn (DAC, 2013)

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores. - Fazal Hameed; Lars Bauer; Jörg Henkel (DATE, 2013)

An H.264 Quad-FullHD low-latency intra video encoder. - Muhammad Usman Karim Khan; Jan Micha Borrmann; Lars Bauer; Muhammad Shafique 001; Jörg Henkel (DATE, 2013)

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. - Hongyan Zhang 004; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich; Jörg Henkel (ITC, 2013)

Test Strategies for Reliable Runtime Reconfigurable Architectures. - Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang 004; Jörg Henkel; Hans-Joachim Wunderlich (IEEE Trans. Computers, 2013)

COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems. - Artjom Grudnitsky; Lars Bauer; Jörg Henkel (CASES, 2014)

Automatic custom instruction identification in memory streaming algorithms. - Martin Haaß; Lars Bauer; Jörg Henkel (CASES, 2014)

Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. - Fazal Hameed; Lars Bauer; Jörg Henkel (DAC, 2014)

Multi-Layer Dependability: From Microarchitecture to Application Level. - Jörg Henkel; Lars Bauer; Hongyan Zhang 004; Semeen Rehman; Muhammad Shafique 001 (DAC, 2014)

GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. - Hongyan Zhang 004; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich; Jörg Henkel (DAC, 2014)

MORP: makespan optimization for processors with an embedded reconfigurable fabric. - Artjom Grudnitsky; Lars Bauer; Jörg Henkel (FPGA, 2014)

Adaptive embedded computing with i-core. - Jörg Henkel; Lars Bauer; Artjom Grudnitsky; Hongyan Zhang 004 (SIGBED Rev., 2014)

Adaptive Energy Management for Dynamically Reconfigurable Processors. - Muhammad Shafique 001; Lars Bauer; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

An approximate compressor for wearable biomedical healthcare monitoring systems. - Farzad Samie; Lars Bauer; Jörg Henkel (CODES+ISSS, 2015)

Adaptive on-the-fly application performance modeling for many cores. - Sebastian Kobbe; Lars Bauer; Jörg Henkel (DATE, 2015)

Online binding of applications to multiple clock domains in shared FPGA-based systems. - Farzad Samie; Lars Bauer; Chih-Ming Hsieh; Jörg Henkel (DATE, 2015)

Floating point acceleration for stream processing applications in dynamically reconfigurable processors. - Lars Bauer; Artjom Grudnitsky; Marvin Damschen; Srinivas Rao Kerekare; Jörg Henkel (ESTIMedia, 2015)

STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. - Hongyan Zhang 004; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich; Jörg Henkel (ICCAD, 2015)

Adaptive multi-layer techniques for increased system dependability. - Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes Maximilian Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich; Hongyan Zhang 004 (it Inf. Technol., 2015)

Resource-awareness on heterogeneous MPSoCs for image processing. - Johny Paul; Walter Stechele; Benjamin Oechslein; Christoph Erhardt; Jens Schedel; Daniel Lohmann; Wolfgang Schröder-Preikschat; Manfred Kröhnert; Tamim Asfour; Éricles Sousa; Vahid Lari; Frank Hannig; et al. (J. Syst. Archit., 2015)

Multicast FullHD H.264 Intra Video Encoder Architecture. - Muhammad Usman Karim Khan; Muhammad Shafique 001; Lars Bauer; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

IoT technologies for embedded computing: a survey. - Farzad Samie; Lars Bauer; Jörg Henkel (CODES+ISSS, 2016)

Distributed QoS management for internet of things under resource constraints. - Farzad Samie; Vasileios Tsoutsouras; Sotirios Xydis; Lars Bauer; Dimitrios Soudris; Jörg Henkel (CODES+ISSS, 2016)

Resource budgeting for reliability in reconfigurable architectures. - Hongyan Zhang 004; Lars Bauer; Jörg Henkel (DAC, 2016)

Computation offloading and resource allocation for low-power IoT edge devices. - Farzad Samie; Vasileios Tsoutsouras; Lars Bauer; Sotirios Xydis; Dimitrios Soudris; Jörg Henkel (WF-IoT, 2016)

Dark silicon management: an integrated and coordinated cross-layer approach. - Santiago Pagani; Lars Bauer; Qingqing Chen 004; Elisabeth Glocker; Frank Hannig; Andreas Herkersdorf; Heba Khdr; Anuj Pathania; Ulf Schlichtmann; Doris Schmitt-Landsiedel; Mark Sagi; Éricles Sousa; et al. (it Inf. Technol., 2016)

Invasive computing for timing-predictable stream processing on MPSoCs. - Stefan Wildermann; Michael Bader; Lars Bauer; Marvin Damschen; Dirk Gabriel; Michael Gerndt; Michael Glaß; Jörg Henkel; Johny Paul; Alexander Pöppl; Sascha Roloff; Tobias Schwarzer; et al. (it Inf. Technol., 2016)

Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors. - Marvin Damschen; Lars Bauer; Jörg Henkel (ACM Trans. Archit. Code Optim., 2016)

Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. - Fazal Hameed; Lars Bauer; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies). - Jörg Henkel; Santiago Pagani; Hussam Amrouch; Lars Bauer; Farzad Samie (DATE, 2017)

Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing. - Alexander Pöppl; Marvin Damschen; Florian Schmaus; Andreas Fried; Manuel Mohr; Matthias Blankertz; Lars Bauer; Jörg Henkel; Wolfgang Schröder-Preikschat; Michael Bader (Euro-Par Workshops, 2017)

Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. - Tanja Harbaum; Christoph Schade; Marvin Damschen; Carsten Tradowsky; Lars Bauer; Jörg Henkel; Jürgen Becker 001 (SoCC, 2017)

CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems. - Marvin Damschen; Lars Bauer; Jörg Henkel (IEEE Embed. Syst. Lett., 2017)

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. - Hongyan Zhang 004; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich; Jörg Henkel (IEEE Trans. Computers, 2017)

Timing Analysis of Tasks on Runtime Reconfigurable Processors. - Marvin Damschen; Lars Bauer; Jörg Henkel (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. - Artjom Grudnitsky; Lars Bauer; Jörg Henkel (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Highly efficient and accurate seizure prediction on constrained IoT devices. - Farzad Samie; Sebastian Paul; Lars Bauer; Jörg Henkel (DATE, 2018)

Distributed Trade-Based Edge Device Management in Multi-Gateway IoT. - Farzad Samie; Vasileios Tsoutsouras; Lars Bauer; Sotirios Xydis; Dimitrios Soudris; Jörg Henkel (ACM Trans. Cyber Phys. Syst., 2018)

Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs. - Enrico Rossi; Marvin Damschen; Lars Bauer; Giorgio C. Buttazzo; Jörg Henkel (ACM Trans. Reconfigurable Technol. Syst., 2018)

DMRM: Distributed Market-Based Resource Management of Edge Computing Systems. - Manolis Katsaragakis; Dimosthenis Masouros; Vasileios Tsoutsouras; Farzad Samie; Lars Bauer; Jörg Henkel; Dimitrios Soudris (DATE, 2019)

Analyses and architectures for mixed-critical systems: industry trends and research perspective. - Lars Bauer; Marvin Damschen; Dirk Ziegenbein; Arne Hamann 001; Alessandro Biondi 001; Giorgio C. Buttazzo; Jörg Henkel (EMSOFT Companion, 2019)

WCET Guarantees for Opportunistic Runtime Reconfiguration. - Marvin Damschen; Lars Bauer; Jörg Henkel (ICCAD, 2019)

From Cloud Down to Things: An Overview of Machine Learning in Internet of Things. - Farzad Samie; Lars Bauer; Jörg Henkel (IEEE Internet Things J., 2019)

Oops: Optimizing Operation-mode Selection for IoT Edge Devices. - Farzad Samie; Vasileios Tsoutsouras; Lars Bauer; Sotirios Xydis; Dimitrios Soudris; Jörg Henkel (ACM Trans. Internet Techn., 2019)

System Software for Resource Arbitration on Future Many-* Architectures. - Florian Schmaus; Sebastian Maier; Tobias Langer; Jonas Rabenstein; Timo Hönig; Wolfgang Schröder-Preikschat; Lars Bauer; Jörg Henkel (IPDPS Workshops, 2020)

Impacts of Mobility Models on RPL-Based Mobile IoT Infrastructures: An Evaluative Comparison and Survey. - Bardia Safaei 001; Ali Asghar Mohammadsalehi; Kimia Talaei Khoosani; Saba Zarbaf; Amir Mahdi Hosseini Monazzah; Farzad Samie; Lars Bauer; Jörg Henkel; Alireza Ejlali (IEEE Access, 2020)

SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory. - Christian Hakert; Kuan-Hsun Chen; Paul R. Genssler; Georg von der Brüggen; Lars Bauer; Hussam Amrouch; Jian-Jia Chen; Jörg Henkel (CoRR, 2020)

Hierarchical Classification for Constrained IoT Devices: A Case Study on Human Activity Recognition. - Farzad Samie; Lars Bauer; Jörg Henkel (IEEE Internet Things J., 2020)

Improved Feature Extraction Method for Sound Recognition Applied to Automatic Sorting of Recycling Wastes. - Tatsuji Munaka; Farzad Samie; Lars Bauer; Jörg Henkel (J. Inf. Process., 2020)

Fast Operation Mode Selection for Highly Efficient IoT Edge Devices. - Farzad Samie; Vasileios Tsoutsouras; Dimosthenis Masouros; Lars Bauer; Dimitrios Soudris; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation. - Hassan Nassar; Lars Bauer; Jörg Henkel (DATE, 2021)

LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs. - Hassan Nassar; Hanna AlZughbi; Dennis R. E. Gnad; Lars Bauer; Mehdi B. Tahoori; Jörg Henkel (ICCAD, 2021)

Agent-based Constraint Solving for Resource Allocation in Manycore Systems. - Volker Wenzel; Lars Bauer; Wolfgang Schröder-Preikschat; Jörg Henkel (CoRR, 2022)

ARMOR: A Reliable and Mobility-Aware RPL for Mobile Internet of Things Infrastructures. - Ali Asghar Mohammad Salehi; Bardia Safaei 001; Amir Mahdi Hosseini Monazzah; Lars Bauer; Jörg Henkel; Alireza Ejlali (IEEE Internet Things J., 2022)

CaPUF: Cascaded PUF Structure for Machine Learning Resiliency. - Hassan Nassar; Lars Bauer; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory. - Christian Hakert; Kuan-Hsun Chen; Horst Schirmeier; Lars Bauer; Paul R. Genssler; Georg von der Brüggen; Hussam Amrouch; Jörg Henkel; Jian-Jia Chen (ACM Trans. Embed. Comput. Syst., 2022)

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. - Jörg Henkel; Lokesh Siddhu; Lars Bauer; Jürgen Teich; Stefan Wildermann; Mehdi B. Tahoori; Mahta Mayahinia; Jerónimo Castrillón; Asif Ali Khan; Hamid Farzaneh; João Paulo C. de Lima; Jian-Jia Chen; et al. (CASES, 2023)

Smart Detection of Obfuscated Thermal Covert Channel Attacks in Many-core Processors. - Jeferson González-Gómez; Mohammed Bakr Sikal; Heba Khdr; Lars Bauer; Jörg Henkel (DAC, 2023)

Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure. - Hassan Nassar; Simon Pankner; Lars Bauer; Jörg Henkel (DAC, 2023)

The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures. - Jeferson González-Gómez; Kevin Cordero-Zuñiga; Lars Bauer; Jörg Henkel (DATE, 2023)

Supporting Dynamic Control-Flow Execution for Runtime Reconfigurable Processors. - Hassan Nassar; Rafik Youssef; Lars Bauer; Jörg Henkel (ICM, 2023)

Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory. - Nils Hölscher; Christian Hakert; Hassan Nassar; Kuan-Hsun Chen; Lars Bauer; Jian-Jia Chen; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Cache-Based Side-Channel Attack Mitigation for Many-Core Distributed Systems via Dynamic Task Migration. - Jeferson González-Gómez; Lars Bauer; Jörg Henkel (IEEE Trans. Inf. Forensics Secur., 2023)

ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF. - Hassan Nassar; Lars Bauer; Jörg Henkel (ACM Trans. Embed. Comput. Syst., 2023)

Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators. - Hassan Nassar; Lars Bauer; Jörg Henkel (IEEE Embed. Syst. Lett., 2023)

Swift-CNN: Leveraging PCM Memory's Fast Write Mode to Accelerate CNNs. - Lokesh Siddhu; Hassan Nassar; Lars Bauer; Christian Hakert; Nils Hölscher; Jian-Jia Chen; Jörg Henkel (IEEE Embed. Syst. Lett., 2023)

HBMorphic: FHE Acceleration via HBM-Enabled Recursive Karatsuba Multiplier on FPGA. - Hassan Nassar; Lars Bauer; Jörg Henkel (FCCM, 2024)

Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels. - Hassan Nassar; Philipp Machauer; Dennis R. E. Gnad; Lars Bauer; Mehdi B. Tahoori; Jörg Henkel (FPGA, 2024)

MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs. - Lilas Alrahis; Hassan Nassar; Jonas Krautter; Dennis Gnad; Lars Bauer; Jörg Henkel; Mehdi B. Tahoori (HOST, 2024)

LightFAt: Mitigating Control-Flow Explosion via Lightweight PMU-Based Control-Flow Attestation. - Jeferson González-Gómez; Hassan Nassar; Lars Bauer; Jörg Henkel (HOST, 2024)

Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications. - Jörg Henkel; Lokesh Siddhu; Hassan Nassar; Lars Bauer; Jian-Jia Chen; Christian Hakert; Tristan Taylan Seidl; Kuan-Hsun Chen; Xiaobo Sharon Hu; Mengyuan Li; Chia-Lin Yang; Ming-Liang Wei (ICCAD, 2024)

DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering. - Hassan Nassar; Philipp Machauer; Lars Bauer; Dennis Gnad; Mehdi Baradaran Tahoori; Jörg Henkel (ICCAD, 2024)

Client-Server Framework for FPGA Acceleration of Fan-Vercauteren-Based Homomorphic Encryption. - Simon Bothe; Hassan Nassar; Lars Bauer; Jörg Henkel (ICM, 2024)

An FPGA-Based RISC-V Instruction Set Extension and Memory Controller for Multi-Level Cell NVM. - Mina Ibrahim; Martel Shokry; Lokesh Siddhu; Lars Bauer; Hassan Nassar; Jörg Henkel (ICM, 2024)

MeMoir: A Software-Driven Covert Channel based on Memory Usage. - Jeferson González-Gómez; Jose Alejandro Ibarra-Campos; Jesus Yamir Sandoval-Morales; Lars Bauer; Jörg Henkel (CoRR, 2024)

Balancing Security and Efficiency: System-Informed Mitigation of Power-Based Covert Channels. - Jeferson González-Gómez; Mohammed Bakr Sikal; Heba Khdr; Lars Bauer; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata. - Hassan Nassar; Jonas Krautter; Lars Bauer; Dennis Gnad; Mehdi B. Tahoori; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems. - Hassan Nassar; Jeferson González-Gómez; Varun Manjunath; Lars Bauer; Jörg Henkel (ASP-DAC, 2025)

Hardware/Software Co-Analysis for Worst Case Execution Time Bounds. - Can Joshua Lehmann; Lars Bauer; Hassan Nassar; Heba Khdr; Jörg Henkel (DATE, 2025)

Turbo-FHE: Accelerating Fully Homomorphic Encryption With FPGA and HBM Integration. - Hassan Nassar; Lars Bauer; Jörg Henkel (IEEE Des. Test, 2025)