Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. - Michael Hübner 001; Michael Ullmann; Lars Braun; A. Klausmann; Jürgen Becker 001 (FPL, 2004)

Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. - Lars Braun; Michael Hübner 001; Jürgen Becker 001; Thomas Perschke; Volker Schatz; Stefan Bach (FPL, 2007)

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. - Michael Hübner 001; Lars Braun; Jürgen Becker 001; Christopher Claus; Walter Stechele (ISVLSI, 2007)

Data reallocation by exploiting FPGA configuration mechanisms. - Oliver Sander; Lars Braun; Michael Hübner 001; Jürgen Becker 001 (ARC, 2008)

Fine grain reconfigurable architectures. - Josef Angermeier; Mateusz Majer; Jürgen Teich; Lars Braun; Tobias Schwalb; Philipp Graf; Michael Hübner 001; Jürgen Becker 001; Enno Lübbers; Marco Platzner; Christopher Claus; Walter Stechele; et al. (FPL, 2008)

Data path driven waveform-like reconfiguration. - Lars Braun; Katarina Paulsson; Herrmann Krömer; Michael Hübner 001; Jürgen Becker 001 (FPL, 2008)

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. - Christopher Claus; Bin Zhang; Walter Stechele; Lars Braun; Michael Hübner 001; Jürgen Becker 001 (FPL, 2008)

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. - Michael Hübner 001; Lars Braun; Diana Göhringer; Jürgen Becker 001 (IPDPS, 2008)

An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. - Alexander Klimm; Lars Braun; Jürgen Becker 001 (IPDPS, 2008)

FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz; Lars Braun; Michael Hübner 001; Jürgen Becker 001 (ARC, 2009)

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture. - Lars Braun; Diana Göhringer; Thomas Perschke; Volker Schatz; Michael Hübner 001; Jürgen Becker 001 (J. Real Time Image Process., 2009)

Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies. - Lars Braun; Tobias Schwalb; Philipp Graf; Michael Hübner 001; Michael Ullmann; Klaus D. Müller-Glaser; Jürgen Becker 001 (Dynamically Reconfigurable Systems, 2010)

Two Dimensional Dynamic Multigrained Reconfigurable Hardware. - Lars Braun; Jürgen Becker 001 (ISVLSI (Selected papers), 2010)

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. - Michael Hübner 001; Joachim Meyer 001; Oliver Sander; Lars Braun; Jürgen Becker 001; Juanjo Noguera; Rodney Stewart (ISVLSI, 2010)

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. - Joachim Meyer 001; Michael Hübner 001; Lars Braun; Oliver Sander; Juanjo Noguera; Rodney Stewart; Jürgen Becker 001 (ISVLSI (Selected papers), 2010)

Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space. - Oliver Sander; Benjamin Glas; Lars Braun; Klaus D. Müller-Glaser; Jürgen Becker 001 (ReConFig, 2010)

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz; Lars Braun; Michael Hübner 001; Jürgen Becker 001 (ACM Trans. Reconfigurable Technol. Syst., 2010)

Run-time resource instantiation for fault tolerance in FPGAs. - Monica Magalhães Pereira; Lars Braun; Michael Hübner 001; Jürgen Becker 001; Luigi Carro (AHS, 2011)

Development of a method for image-based motion estimation of a VTOL-MAV on FPGA. - Natalie Frietsch; I. Pashkovskiy; Gert F. Trommer; Lars Braun; Matthias Birk; Michael Hübner 001; Jürgen Becker 001 (DASIP, 2011)

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. - Joachim Meyer 001; Juanjo Noguera; Michael Hübner 001; Lars Braun; Oliver Sander; R. M. Gil; Rodney Stewart; Jürgen Becker 001 (DATE, 2011)

A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker. - Matthias Rümmele-Werner; Thomas Perschke; Lars Braun; Michael Hübner 001; Jürgen Becker 001 (ISCAS, 2011)

Dynamic Processor Reconfiguration. - Michael Hübner 001; Carsten Tradowsky; Diana Göhringer; Lars Braun; Florian Thoma; Jörg Henkel; Jürgen Becker 001 (ReConFig, 2011)

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices. - Oliver Sander; Benjamin Glas; Lars Braun; Klaus D. Müller-Glaser; Jürgen Becker 001 (Int. J. Reconfigurable Comput., 2012)

Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems. - Lars Braun (2013)