A formal approach to nonlinear analog circuit verification. - Lars Hedrich; Erich Barke (ICCAD, 1995)

Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. - Carsten Borchers; Lars Hedrich; Erich Barke (DAC, 1996)

Ansätze zur formalen Verifikation analoger Schaltungen. - Lars Hedrich (VDI-Verlag, 1997)

A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. - Lars Hedrich; Erich Barke (DATE, 1998)

On the Simplification of Nonlinear DAE Systems in Analog Circuit Design. - Tim Wichmann; Ralf Popp; Walter Hartong; Lars Hedrich (CASC, 1999)

A current driven routing and verification methodology for analog applications. - Thorsten Adler; Hiltrud Brocke; Lars Hedrich; Erich Barke (DAC, 2000)

On Discrete Modeling and Model Checking for Nonlinear Analog Systems. - Walter Hartong; Lars Hedrich; Erich Barke (CAV, 2002)

Model checking algorithms for analog verification. - Walter Hartong; Lars Hedrich; Erich Barke (DAC, 2002)

An Approach to Model Checking for Nonlinear Analog Systems. - Walter Hartong; Lars Hedrich; Erich Barke (DATE, 2002)

Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. - Ralf Popp; Joerg Oehmen; Lars Hedrich; Erich Barke (DATE, 2002)

Analog circuit sizing based on formal methods using affine arithmetic. - Andreas C. Lemke; Lars Hedrich; Erich Barke (ICCAD, 2002)

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. - Lutz Näthke; Volodymyr Burkhay; Lars Hedrich; Erich Barke (DATE, 2004)

Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. - Darius Grabowski; Daniel Platte; Lars Hedrich; Erich Barke (FAC, 2005)

An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. - Xiaoying Wang 001; Lars Hedrich (ASP-DAC, 2006)

Hierarchical exploration and selection of transistor-topologies for analog circuit design. - Xiaoying Wang 001; Lars Hedrich (ISCAS, 2006)

A case study on applying bounded model checking to analog circuit verification. - Alexander Jesser; Markus Wedler; Lars Hedrich; Wolfgang Kunz (MBMV, 2006)

Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. - Ralf Klausen; Lars Hedrich; Erich Barke (MBMV, 2006)

A symbolic approach for mixed-signal model checking. - Alexander Jesser; Lars Hedrich (ASP-DAC, 2008)

Model Checking of Analog Systems using an Analog Specification Language. - Sebastian Steinhorst; Lars Hedrich (DATE, 2008)

Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. - Xiaoying Wang 001; Lars Hedrich (DATE, 2008)

Advanced Assertion-Based Design for Mixed-Signal Verification. - Alexander Jesser; Stefan Lämmermann; Alexander Pacholik; Roland Weiss; Jürgen Ruf; Lars Hedrich; Wolfgang Fengler 001; Thomas Kropf; Wolfgang Rosenstiel (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Formal approaches to analog circuit verification. - Erich Barke; Darius Grabowski; Helmut Graeb; Lars Hedrich; Stefan Heinen; Ralf Popp; Sebastian Steinhorst; Yifan Wang 001 (DATE, 2009)

Towards assertion-based verification of heterogeneous system designs. - Stefan Lämmermann; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel; Alexander Viehl; Alexander Jesser; Lars Hedrich (DATE, 2010)

Improving verification coverage of analog circuit blocks by state space-guided transient simulation. - Sebastian Steinhorst; Lars Hedrich (ISCAS, 2010)

Advanced methods for equivalence checking of analog circuits with strong nonlinearities. - Sebastian Steinhorst; Lars Hedrich (Formal Methods Syst. Des., 2010)

Design and architectures for dependable embedded systems. - Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann 001; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; et al. (CODES+ISSS, 2011)

Automated constraint-driven topology synthesis for analog circuits. - Oliver Mitea; Markus Meissner; Lars Hedrich; P. Jores (DATE, 2011)

A machine-readable specification of analog circuits for integration into a validation flow. - Mingyu Ma 002; Lars Hedrich; Christian Sporrer (FDL, 2011)

Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. - Oliver Mitea; Markus Meissner; Lars Hedrich (VLSI-SoC, 2011)

Fast isomorphism testing for a graph-based analog circuit synthesis framework. - Markus Meissner; Oliver Mitea; Linda Luy; Lars Hedrich (DATE, 2012)

Analog assertion-based verification on partial state space representations using ASL. - Sebastian Steinhorst; Lars Hedrich (FDL, 2012)

Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits. - Sebastian Steinhorst; Lars Hedrich (ICCAD, 2012)

Detection and Defense Strategies against Attacks on an Artificial Hormone System Running on a Mixed Signal Chip. - Christoph Leineweber; Mathias Pacher; Benjamin Betting; Julius von Rosen; Uwe Brinkschulte; Lars Hedrich (ISORC, 2012)

Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification. - Sebastian Steinhorst; Lars Hedrich (VLSI-SoC, 2012)

A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip. - Benjamin Betting; Julius von Rosen; Lars Hedrich; Uwe Brinkschulte (ARCS, 2013)

Modular system-level architecture for concurrent cell balancing. - Matthias Kauer; Swaminathan Naranayaswami; Sebastian Steinhorst; Martin Lukasiewycz; Samarjit Chakraborty; Lars Hedrich (DAC, 2013)

ASDeX: a formal specification for analog circuit enabling a full automated design validation. - Mingyu Ma 002; Lars Hedrich; Christian Sporrer (Des. Autom. Embed. Syst., 2014)

Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores. - Julius von Rosen; Markus Meissner; Lars Hedrich (DATE, 2015)

Ageing simulation of analogue circuits and systems using adaptive transient evaluation. - Felix Salfelder; Lars Hedrich (DATE, 2015)

Method for system level vibro-acoustic gear modeling and simulation of electro-mechanical drive trains. - Tim Dackermann; Rolando Dölling; Lars Hedrich (ISSE, 2015)

A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture. - Julius von Rosen; Felix Salfelder; Lars Hedrich; Benjamin Betting; Uwe Brinkschulte (Integr., 2015)

FEATS: Framework for Explorative Analog Topology Synthesis. - Markus Meissner; Lars Hedrich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. - Erich Barke; Andreas Furtig; Georg Glaeser; Christoph Grimm 001; Lars Hedrich; Stefan Heinen; Eckhard Hennig; Hyun-Sek Lukas Lee; Wolfgang Nebel; Gregor Nitsche; Markus Olbrich; Carna Radojicic; et al. (DATE, 2016)

Feature based state space coverage of analog circuits. - Andreas Furtig; Sebastian Steinhorst; Lars Hedrich (FDL, 2016)

Novel metrics for Analog Mixed-Signal coverage. - Andreas Furtig; Georg Glaeser; Christoph Grimm 001; Lars Hedrich; Stefan Heinen; Hyun-Sek Lukas Lee; Gregor Nitsche; Markus Olbrich; Carna Radojicic; Fabian Speicher (DDECS, 2017)

Comparing code coverage metrics for analog behavioral models. - Andreas Furtig; Moritz Paschke; Lars Hedrich (SMACD, 2017)

Real-time emulation of block-based analog circuits on an FPGA. - Philipp Tertel; Lars Hedrich (Integr., 2018)

Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata. - Ahmad Tarraf; Lars Hedrich (DATE, 2019)

Multi-agent Learning for Energy-Aware Placement of Autonomous Vehicles. - Ömer Ibrahim Erduran; Mirjam Minor; Lars Hedrich; Ahmad Tarraf; Frederik Ruehl; Hans Schroth (ICMLA, 2019)

Numerical Simulations of Vibro-acoustic Behaviors related to Drive Train Assemblies. - Yashwant Kolluru; Rolando Dölling; Lars Hedrich (ISSE, 2019)

Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices. - Ahmad Tarraf; Lars Hedrich (SMACD, 2019)

Establishing Reachset Conformance for the Formal Analysis of Analog Circuits. - Niklas Kochdumper; Ahmad Tarraf; Malgorzata Rechmal; Markus Olbrich; Lars Hedrich; Matthias Althoff (ASP-DAC, 2020)

Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. - Ahmad Tarraf; Lars Hedrich; Niklas Kochdumper; Malgorzata Rechmal-Lesse; Markus Olbrich (ISVLSI, 2020)

From transistor level to cyber physical/hybrid systems: Formal verification using automatic compositional abstraction. - Ahmad Tarraf; Lars Hedrich (it Inf. Technol., 2020)

Towards Compositional Abstraction of Analog Neuronal Networks. - Ahmad Tarraf; Lars Hedrich (CCWC, 2021)

Energy efficient convolutional neural networks for arrhythmia detection. - Nikoletta Katsaouni; Florian Aul; Lukas Krischker; Sascha Schmalhofer; Lars Hedrich; Marcel H. Schulz (Array, 2022)

Debugging Low Power Analog Neural Networks for Edge Computing. - Sascha Schmalhofer; Marwin Möller; Nikoletta Katsaouni; Marcel H. Schulz; Lars Hedrich (DATE, 2023)

Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. - Kemal Çaglar Coskun; Muhammad Hassan 002; Lars Hedrich; Rolf Drechsler (DAC, 2024)

Identifying Undetectable Defects Using Equivalence Checking. - Lars Hedrich; Inga Abel; Jaafar Mejri; Vladimir A. Zivkovic (ITC, 2024)

Formal Verification of Nonlinear Analog Circuits using State Space-Based Model Order Reduction. - Yasmine Abu-Haeyeh; Lars Hedrich (SMACD, 2024)

Formally Verifying Analog Neural Networks with Device Mismatch Variations. - Yasmine Abu-Haeyeh; Thomas Bartelsmeier; Tobias Ladner; Matthias Althoff; Lars Hedrich; Markus Olbrich (DATE, 2025)

Behavioral Modeling of Analog Neural Networks Inference Circuits. - Yasmine Abu-Haeyeh; Sascha Schmalhofer; Lars Hedrich (SMACD, 2025)

NNHC - a Neural Network to Hardware Compiler. - Sascha Schmalhofer; Yasmine Abu-Haeyeh; Lars Hedrich (SMACD, 2025)