Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (Int. J. Appl. Math. Comput. Sci., 2007)

Logic Synthesis for Compositional Microprogram Control Units - Alexander Barkalov 001; Larysa Titarenko (Springer, 2008)

Logic Synthesis for FSM-Based Control Units - Alexander Barkalov 001; Larysa Titarenko (Springer, 2009)

Microprogram control unit with code sharing and extended microinstruction format. - Alexander Barkalov 001; Larysa Titarenko; Jacek Bieganowski (EWDTS, 2010)

Hardware reduction for FSM - Based control units using PAL technology. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (EWDTS, 2010)

Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (EWDTS, 2010)

Reduction in the number of LUT elements for control units with code sharing. - Alexander Barkalov 001; Larysa Titarenko; Jacek Bieganowski (Int. J. Appl. Math. Comput. Sci., 2010)

Synthesis of control unit with refined state encoding for CPLD devices. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (EWDTS, 2011)

Hardware reduction for matrix circuit of control Moore automaton. - Alexander Barkalov 001; Larysa Titarenko; Olena Hebda (EWDTS, 2011)

Optimization of microprogram control unit with code sharing. - Alexander Barkalov 001; Larysa Titarenko; Lukasz Smolinski (EWDTS, 2011)

Design of microprogrammed controllers to be implemented in FPGAs. - Remigiusz Wisniewski; Alexander Barkalov 001; Larysa Titarenko; Wolfgang A. Halang (Int. J. Appl. Math. Comput. Sci., 2011)

Control and Adaptation in Telecommunication Systems - Mathematical Foundations - Vladimir Popovskij; Alexander Barkalov 001; Larysa Titarenko (Springer, 2011)

Compositional microprogram control unit with operational automaton of transitions. - Alexander Barkalov 001; Roman Babakov; Larysa Titarenko (EWDTS, 2013)

Hardware reduction for compositional microprogram control unit dedicated for CPLD systems. - Alexander Barkalov 001; Larysa Titarenko; Lukasz Smolinski (EWDTS, 2013)

Matrix implementation of Moore FSM with nonstandard presentation of state codes. - Larysa Titarenko; Olena Hebda (EWDTS, 2013)

Design of moore finite state machine with extended state codes. - Larysa Titarenko; Olena Hebda; Alexander Barkalov 001 (ITI, 2013)

Synthesis of Moore Finite State Machines Based on Pseudoequivalent States. - Alexander Barkalov 001; Slawomir Chmielewski; Larysa Titarenko (PDeS, 2013)

Design of FPGA-Based Moore FMSs with Counters. - Alexander Barkalov 001; Larysa Titarenko; Jacek Bieganowski (PDeS, 2013)

EMB - Based Design of Mealy FSM. - Alexander Barkalov 001; Larysa Titarenko; Malgorzata Kolopienczyk (PDeS, 2013)

Synthesis of PLA-Based Moore FSM with Unconventional Presentation of State Codes. - Larysa Titarenko; Olena Hebda; Alexander Barkalov 001 (PDeS, 2013)

Hardware Reduction in FPGA-Based Moore FSM. - Alexander Barkalov 001; Larysa Titarenko; Raisa Malcheva; Kyryll Soldatov (J. Circuits Syst. Comput., 2013)

Hardware reduction for RAM-based Moore FSMs. - Malgorzata Kolopienczyk; Alexander Barkalov 001; Larysa Titarenko (HSI, 2014)

Design of Moore finite state machine with coding space stretching. - Larysa Titarenko; Olena Hebda; Alexander Barkalov 001 (HSI, 2014)

Hardware Reduction in CPLD-Based Moore FSM. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (J. Circuits Syst. Comput., 2014)

Designing Moore FSM with Transformation of State Codes. - Kamil Mielcarek; Alexander Barkalov 001; Larisa Titarenko (CISIM, 2017)

Designing HFPGA-based FSMs with counters. - Alexander Barkalov 001; Larysa Titarenko; Jacek Bieganowski (MIXDES, 2017)

CloudBus protocol hardware multi-converter gateway for distributed embedded systems. - Kazimierz Krzywicki; Alexander Barkalov 001; Grzegorz Andrzejewski; Larysa Titarenko; Malgorzata Kolopienczyk (MIXDES, 2017)

Designing HFPGA-based Mealy FSMs with transformation of output functions. - Kamil Mielcarek; Alexander Barkalov 001; Larysa Titarenko (MIXDES, 2017)

Code sharing in CPLD-based Moore FSMs. - Alexander Barkalov 001; Larysa Titarenko; Jacek Bieganowski (MOCAST, 2017)

Designing Moore FSM with extended class codes. - Kamil Mielcarek; Alexander Barkalov 001; Larysa Titarenko (MOCAST, 2017)

Design of EMB-Based Moore FSMs. - Malgorzata Kolopienczyk; Larysa Titarenko; Alexander Barkalov 001 (J. Circuits Syst. Comput., 2017)

Twofold State Assignment for LUT-based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (MIXDES, 2018)

Design of FPGA-based Mealy FSMs with Counters. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Slawomir Chmielewski (MIXDES, 2018)

Encoding of Terms in LUT-based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Malgorzata Mazurkiewicz; Kamil Mielcarek (MIXDES, 2018)

Design of CPLD-based mealy FSMs with counters. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (MOCAST, 2018)

Twofold state assignment for FPGA-based mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (MOCAST, 2018)

Hardware Reduction for Lut-Based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (Int. J. Appl. Math. Comput. Sci., 2018)

Decreasing Number of LUTs for Moore FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Kazimierz Krzywicki; Wojciech Zajac (MIXDES, 2019)

Designing FPGA-Based Mealy FSMs with Two Levels of Logic. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (MOCAST, 2019)

Encoding of Microoperations in FPGA-Based Moore FSMs. - Alexander Barkalov 001; Larysa Titarenko; Malgorzata Mazurkiewicz; Kamil Mielcarek (MOCAST, 2019)

Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (J. Circuits Syst. Comput., 2019)

Improving Characteristics of LUT-Based Moore FSMs. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (IEEE Access, 2020)

Improving characteristics of LUT-based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (Int. J. Appl. Math. Comput. Sci., 2020)

Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Slawomir Chmielewski (Springer, 2020)

IPNES - Interpreted Petri Net for Embedded Systems. - Kazimierz Krzywicki; Grzegorz Andrzejewski; Wojciech Zajac; Tomasz Królikowski; Alexander Barkalov 001; Larysa Titarenko (KES, 2021)

Improving Characteristics of FSMs With Mixed Codes of Outputs. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski; Kamil Mielcarek (IEEE Access, 2022)

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections. - Alexander Barkalov 001; Larysa Titarenko; Malgorzata Mazurkiewicz (Int. J. Appl. Math. Comput. Sci., 2022)

Reducing LUT Count for Mealy FSMs With Transformation of States. - Alexander A. Barkalov; Larysa Titarenko; Kamil Mielcarek (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Malgorzata Mazurkiewicz; Elzbieta Kawecka (Springer, 2022)

Hardware Reduction for FSMs With Extended State Codes. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Malgorzata Mazurkiewicz (IEEE Access, 2024)

Reducing the number of LUTs for Mealy FSMs with state transformation. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (Int. J. Appl. Math. Comput. Sci., 2024)

Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores. - Larysa Titarenko; Vyacheslav Kharchenko; Vadym Puidenko; Artem Perepelitsyn; Alexander Barkalov 001 (Comput., 2024)