Logarithmic time cost optimal parallel sorting is not yet fast in practice!. - Lasse Natvig (SC, 1990)

Compile and Runtime Padding: An Approach to Realising Synchronous MIMD Execution. - Lasse Natvig (IFIP Congress (1), 1994)

Simulating Parallel Architectures with BSPlab. - Lasse Natvig (HPCN Europe, 2001)

Experience from a 450 Students/Year Course on Digital Logic and Computer Fundamentals using FPGAs and mu-Controllers. - Tormod Njølstad; Lasse Natvig (MSE, 2001)

Age of computers: game-based teaching of computer fundamentals. - Lasse Natvig; Steinar Line (ITiCSE, 2004)

Cache Write-Back Schemes for Embedded Destructive-Read DRAM. - Haakon Dybdahl; Marius Grannæs; Lasse Natvig (ARCS, 2006)

Master-Slave Tasking on Asymmetric Networks. - Cyril Banino-Rokkones; Olivier Beaumont; Lasse Natvig (Euro-Par, 2006)

A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. - Haakon Dybdahl; Per Stenström; Lasse Natvig (HiPC, 2006)

Destructive-read in embedded DRAM, impact on power consumption. - Haakon Dybdahl; Per Gunnar Kjeldsberg; Marius Grannæs; Lasse Natvig (J. Embed. Comput., 2006)

An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. - Haakon Dybdahl; Per Stenström; Lasse Natvig (SIGARCH Comput. Archit. News, 2007)

Towards an Intelligent Environment for Programming Multi-core Computing Systems. - Sabri Pllana; Siegfried Benkner; Eduard Mehofer; Lasse Natvig; Fatos Xhafa (Euro-Par Workshops, 2008)

Low-cost open-page prefetch scheduling in chip multiprocessors. - Marius Grannæs; Magnus Jahre; Lasse Natvig (ICCD, 2008)

A light-weight fairness mechanism for chip multiprocessor memory systems. - Magnus Jahre; Lasse Natvig (Conf. Computing Frontiers, 2009)

A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. - Magnus Jahre; Marius Grannæs; Lasse Natvig (HPCC, 2009)

A compulsory yet motivating question/answer game to teach computer fundamentals. - Lasse Natvig; Guttorm Sindre; Asbjørn Djupdal (Comput. Appl. Eng. Educ., 2009)

Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. - Guttorm Sindre; Lasse Natvig; Magnus Jahre (IEEE Trans. Educ., 2009)

Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. - Marius Grannæs; Magnus Jahre; Lasse Natvig (HiPEAC, 2010)

DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. - Magnus Jahre; Marius Grannæs; Lasse Natvig (HiPEAC, 2010)

Mixed-Precision Parallel Linear Programming Solver. - Mujahed Eleyat; Lasse Natvig (SBAC-PAD, 2010)

Computational Computer Architecture Research at NTNU. - Magnus Jahre; Lasse Natvig (ERCIM News, 2010)

Implementation of a linear programming solver on the Cell BE processor. - Mujahed Eleyat; Lasse Natvig (ICCS, 2010)

Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. - Marius Grannæs; Magnus Jahre; Lasse Natvig (ARCS, 2011)

Cache-Aware Matrix Multiplication on Multicore Systems for IPM-based LP Solvers. - Mujahed Eleyat; Lasse Natvig; Jørn Amundsen (FedCSIS, 2011)

Parallel algorithms for the maximum flow problem with minimum lot sizes. - Mujahed Eleyat; Dag Haugland; Magnus Lie Hetland; Lasse Natvig (OR, 2011)

Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. - Marius Grannæs; Magnus Jahre; Lasse Natvig (J. Instr. Level Parallelism, 2011)

A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. - Magnus Jahre; Lasse Natvig (Trans. High Perform. Embed. Archit. Compil., 2011)

Performance and Energy Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor. - Abdullah Al Hasib; Per Gunnar Kjeldsberg; Lasse Natvig (Euro-Par Workshops, 2012)

Case Studies of Multi-core Energy Efficiency in Task Based Programs. - Hallgeir Lien; Lasse Natvig; Abdullah Al Hasib; Jan Christian Meyer (ICT-GLOW, 2012)

Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors. - Juan M. Cebrian; Lasse Natvig; Jan Christian Meyer (SC Companion, 2012)

IPM based sparse LP solver on a heterogeneous processor. - Mujahed Eleyat; Lasse Natvig (Comput. Manag. Sci., 2012)

Temperature effects on on-chip energy measurements. - Juan M. Cebrian; Lasse Natvig (IGCC, 2013)

Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. - Alexandru C. Iordan; Magnus Jahre; Lasse Natvig (ICCS, 2013)

On the energy footprint of task based parallel applications. - Alexandru C. Iordan; Magnus Jahre; Lasse Natvig (HPCS, 2013)

Energy-Efficient Sparse Matrix Autotuning with CSX - A Trade-off Study. - Jan Christian Meyer; Juan M. Cebrian; Lasse Natvig; Vasileios Karakasis; Dimitris Siakavaras; Konstantinos Nikas (IPDPS Workshops, 2013)

Victim Selection Policies for Intel TBB: Overheads and Energy Footprint. - Alexandru C. Iordan; Magnus Jahre; Lasse Natvig (ARCS, 2014)

Load scheduling in smart buildings with bidirectional energy trading. - Abdullah Al Hasib; Nikita Nikitin; Lasse Natvig (IPCCC, 2014)

Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks. - Juan M. Cebrian; Magnus Jahre; Lasse Natvig (ISPASS, 2014)

Performance and energy impact of parallelization and vectorization techniques in modern microprocessors. - Juan M. Cebrian; Lasse Natvig; Jan Christian Meyer (Computing, 2014)

V-PFORDelta: Data Compression for Energy Efficient Computation of Time Series. - Abdullah Al Hasib; Juan M. Cebrian; Lasse Natvig (HiPC, 2015)

Cost-comfort balancing in a smart residential building with bidirectional energy trading. - Abdullah Al Hasib; Nikita Nikitin; Lasse Natvig (SustainIT, 2015)

ParVec: vectorizing the PARSEC benchmark suite. - Juan M. Cebrian; Magnus Jahre; Lasse Natvig (Computing, 2015)

Climbing Mont Blanc - A Training Site for Energy Efficient Programming on Heterogeneous Multicore Processors. - Lasse Natvig; Torbjørn Follan; Simen Støa; Sindre Magnussen; Antonio García-Guirado (CoRR, 2015)

Tuning the victim selection policy of Intel TBB. - Alexandru C. Iordan; Magnus Jahre; Lasse Natvig (J. Syst. Archit., 2015)

A systematic approach to automated construction of power emulation models. - Benjamin A. Bjørnseth; Asbjørn Djupdal; Lasse Natvig (DATE, 2016)

Transient Temperature Prediction for Aging Thermal Sensors Using Artificial Neural Network. - Kameswar Rao Vaddina; Juan M. Cebrian; Lasse Natvig (PDP, 2016)

Efficient array slicing on the Intel Xeon Phi coprocessor. - Benjamin Andreassen Bjørnseth; Jan Christian Meyer; Lasse Natvig (ARRAY@PLDI, 2017)

Make software harder. - Benjamin A. Bjørnseth; Jan Christian Meyer; Lasse Natvig (CF, 2018)

Proof-of-Concept Examples of Performance-Transparent Programming Models. - Benjamin Andreassen Bjørnseth; Jan Christian Meyer; Lasse Natvig (CoRR, 2018)

A vectorized k-means algorithm for compressed datasets: design and experimental analysis. - Abdullah Al Hasib; Juan M. Cebrian; Lasse Natvig (J. Supercomput., 2018)

Scalability analysis of AVX-512 extensions. - Juan M. Cebrian; Lasse Natvig; Magnus Jahre (J. Supercomput., 2020)

FOMOsim: An open-source simulator for rigorous analysis of micromobility planning problems. - Steffen J. S. Bakker; Mohamed Ben Ahmed; Asbjørn Djupdal; Lasse Natvig; Henrik Andersson; Magnus Jahre; Kjetil Fagerholt (Expert Syst. Appl., 2025)