Self-Testing of Embedded RAMs. - Zuhi Sun; Laung-Terng Wang (ITC, 1984)

Circuits for Pseudo-Exhaustive Test Pattern Generation. - Laung-Terng Wang; Edward J. McCluskey (ITC, 1986)

A Hybrid Design of Maximum-Length Sequence Generators. - Laung-Terng Wang; Edward J. McCluskey (ITC, 1986)

Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. - Laung-Terng Wang; Edward J. McCluskey (IEEE Trans. Computers, 1986)

Linear Feedback Shift Register Design Using Cyclic Codes. - Laung-Terng Wang; Edward J. McCluskey (IEEE Trans. Computers, 1988)

Hybrid designs generating maximum-length sequences. - Laung-Terng Wang; Edward J. McCluskey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Circuits for pseudoexhaustive test pattern generation. - Laung-Terng Wang; Edward J. McCluskey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

On per-test fault diagnosis using the X-fault model. - Xiaoqing Wen; Tokiharu Miyoshi; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (ICCAD, 2004)

VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. - Laung-Terng Wang; Khader S. Abdel-Hafez; Shianling Wu; Xiaoqing Wen; Hiroshi Furukawa; Fei-Sheng Hsu; Shyh-Horng Lin; Sen-Wei Tsai (ITC, 2004)

At-Speed Logic BIST for IP Cores. - B. Cheon; E. Lee; Laung-Terng Wang; Xiaoqing Wen; Po-Ching Hsu; Jin Woo Cho; J. Park; Hao-Jan Chao; Shianling Wu (DATE, 2005)

At-Speed Logic BIST Architecture for Multi-Clock Designs. - Laung-Terng Wang; Xiaoqing Wen; Po-Ching Hsu; Shianling Wu; Jonhson Guo (ICCD, 2005)

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. - Laung-Terng Wang; Khader S. Abdel-Hafez; Xiaoqing Wen; Boryau Sheu; Shianling Wu; Shyh-Horng Lin; Ming-Tung Chang (ITC, 2005)

Low-capture-power test generation for scan-based at-speed testing. - Xiaoqing Wen; Yoshiyuki Yamashita; Shohei Morishima; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (ITC, 2005)

Test compression and logic BIST at your fingertips. - Shianling Wu; Laung-Terng Wang; Jin Woo Cho; Zhigang Jiang; Boryau Sheu (ITC, 2005)

On Low-Capture-Power Test Generation for Scan Testing. - Xiaoqing Wen; Yoshiyuki Yamashita; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (VTS, 2005)

Efficient Test Set Modification for Capture Power Reduction. - Xiaoqing Wen; Tatsuya Suzuki; Seiji Kajihara; Kohei Miyase; Yoshihiro Minamoto; Laung-Terng Wang; Kewal K. Saluja (J. Low Power Electron., 2005)

Test data compression based on clustered random access scan. - Yu Hu 001; Cheng Li; Jia Li 022; Yinhe Han 001; Xiaowei Li 001; Wei Wang; Huawei Li 001; Laung-Terng Wang; Xiaoqing Wen (ATS, 2006)

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. - Xiaoqing Wen; Kohei Miyase; Tatsuya Suzuki; Yuta Yamato; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja (ICCD, 2006)

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. - Hiroshi Furukawa; Xiaoqing Wen; Laung-Terng Wang; Boryau Sheu; Zhigang Jiang; Shianling Wu (ITC, 2006)

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. - Xiaoqing Wen; Seiji Kajihara; Kohei Miyase; Tatsuya Suzuki; Kewal K. Saluja; Laung-Terng Wang; Khader S. Abdel-Hafez; Kozo Kinoshita (VTS, 2006)

A Per-Test Fault Diagnosis Method Based on the X-Fault Model. - Xiaoqing Wen; Seiji Kajihara; Kohei Miyase; Yuta Yamato; Kewal K. Saluja; Laung-Terng Wang; Kozo Kinoshita (IEICE Trans. Inf. Syst., 2006)

A New Method for Low-Capture-Power Test Generation for Scan Testing. - Xiaoqing Wen; Yoshiyuki Yamashita; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (IEICE Trans. Inf. Syst., 2006)

An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing. - Xiaoxin Fan; Yu Hu 001; Laung-Terng Wang (ATS, 2007)

Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. - Yasuharu Kohiyama; C. P. Ravikumar; Yasuo Sato; Laung-Terng Wang; Yervant Zorian (ATS, 2007)

A novel scheme to reduce power supply noise for high-quality at-speed scan testing. - Xiaoqing Wen; Kohei Miyase; Seiji Kajihara; Tatsuya Suzuki; Yuta Yamato; Patrick Girard 001; Yuji Ohsumi; Laung-Terng Wang (ITC, 2007)

A Novel ATPG Method for Capture Power Reduction during Scan Testing. - Xiaoqing Wen; Seiji Kajihara; Kohei Miyase; Tatsuya Suzuki; Kewal K. Saluja; Laung-Terng Wang; Kozo Kinoshita (IEICE Trans. Inf. Syst., 2007)

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. - Hiroshi Furukawa; Xiaoqing Wen; Kohei Miyase; Yuta Yamato; Seiji Kajihara; Patrick Girard 001; Laung-Terng Wang; Mohammad Tehranipoor (ATS, 2008)

Practical Challenges in Logic BIST Implementation. - Shianling Wu; Hiroshi Furukawa; Boryau Sheu; Laung-Terng Wang; Hao-Jan Chao; Lizhen Yu; Xiaoqing Wen; Michio Murakami (ATS, 2008)

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. - Shianling Wu; Laung-Terng Wang; Zhigang Jiang; Jiayong Song; Boryau Sheu; Xiaoqing Wen; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Ravi Apte (DFT, 2008)

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. - Laung-Terng Wang; Ravi Apte; Shianling Wu; Boryau Sheu; Kuen-Jong Lee; Xiaoqing Wen; Wen-Ben Jone; Chia-Hsien Yeh; Wei-Shin Wang; Hao-Jan Chao; Jianghao Guo; Jinsong Liu; et al. (ITC, 2008)

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. - Laung-Terng Wang; Xiaoqing Wen; Shianling Wu; Zhigang Wang; Zhigang Jiang; Boryau Sheu; Xinli Gu (IEEE Des. Test Comput., 2008)

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. - Xiaoqing Wen; Kohei Miyase; Tatsuya Suzuki; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (J. Electron. Test., 2008)

Logic Testing. - Laung-Terng Wang; Charles E. Stroud; Kwang-Ting (Tim) Cheng (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Analysis of Resistive Bridging Defects in a Synchronizer. - Hyoung-Kook Kim; Wen-Ben Jone; Laung-Terng Wang; Shianling Wu (Asian Test Symposium, 2009)

Logic BIST Architecture for System-Level Test and Diagnosis. - Jun Qian; Xingang Wang; Qinfu Yang; Fei Zhuang; Junbo Jia; Xiangfeng Li; Yuan Zuo; Jayanth Mekkoth; Jinsong Liu; Hao-Jan Chao; Shianling Wu; Huafeng Yang; et al. (Asian Test Symposium, 2009)

Analysis of Resistive Open Defects in a Synchronizer. - Hyoung-Kook Kim; Wen-Ben Jone; Laung-Terng Wang (DFT, 2009)

Turbo1500: Core-Based Design for Test and Diagnosis. - Laung-Terng Wang; Ravi Apte; Shianling Wu; Boryau Sheu; Wen-Ben Jone; Jianghao Guo; Kuen-Jong Lee; Wei-Shin Wang; Xiaoqing Wen; Hao-Jan Chao; Jinsong Liu; Yanlong Niu; et al. (IEEE Des. Test Comput., 2009)

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Lizhen Yu; Hiroshi Furukawa; Xiaoqing Wen; Wen-Ben Jone; Nur A. Touba; FeiFei Zhao; Jinsong Liu; Hao-Jan Chao; Fangfang Li; Zhigang Jiang (DFT, 2010)

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. - Lizhen Yu; Jeffrey Hung; Boryau Sheu; Bill Huynh; Loc Nguyen; Shianling Wu; Laung-Terng Wang; Xiaoqing Wen (DFT, 2010)

CSER: BISER-based concurrent soft-error resilience. - Laung-Terng Wang; Nur A. Touba; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; James Chien-Mo Li (VTS, 2010)

Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer. - Hyoung-Kook Kim; Wen-Ben Jone; Laung-Terng Wang (J. Electron. Test., 2010)

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. - Kohei Miyase; Xiaoqing Wen; Hiroshi Furukawa; Yuta Yamato; Seiji Kajihara; Patrick Girard 001; Laung-Terng Wang; Mohammad Tehranipoor (IEICE Trans. Inf. Syst., 2010)

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. - Laung-Terng Wang; Xiaoqing Wen; Shianling Wu; Hiroshi Furukawa; Hao-Jan Chao; Boryau Sheu; Jianghao Guo; Wen-Ben Jone (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A novel scan segmentation design method for avoiding shift timing failure in scan testing. - Yuta Yamato; Xiaoqing Wen; Michael A. Kochte; Kohei Miyase; Seiji Kajihara; Laung-Terng Wang (ITC, 2011)

Luncheon Speaker: "Introduction to SoC testing". - Laung-Terng Wang (SoCC, 2011)

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Zhigang Jiang; Lang Tan; Yu Zhang; Yu Hu 001; Wen-Ben Jone; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Lizhen Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Physical-design-friendly hierarchical logic built-in self-test - A case study. - Kelvin Nelson; Jaga Shanmugavadivelu; Jayanth Mekkoth; Venkat Ghanta; Jun Wu; Fei Zhuang; Hao-Jan Chao; Shianling Wu; Jie Rao; Lizhen Yu; Laung-Terng Wang (ISQED, 2012)

On pinpoint capture power management in at-speed scan test generation. - Xiaoqing Wen; Y. Nishida; Kohei Miyase; Seiji Kajihara; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (ITC, 2012)

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Wen-Ben Jone; Michael S. Hsiao; Fangfang Li; James Chien-Mo Li; Jiun-Lang Huang (ACM Trans. Design Autom. Electr. Syst., 2012)

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing. - Dong Xiang; Zhen Chen; Laung-Terng Wang (ACM Trans. Design Autom. Electr. Syst., 2012)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. - Akihiro Tomita; Xiaoqing Wen; Yasuo Sato; Seiji Kajihara; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (Asian Test Symposium, 2013)

A circular pipeline processing based deterministic parallel test pattern generator. - Kuen-Wei Yeh; Jiun-Lang Huang; Hao-Jan Chao; Laung-Terng Wang (ITC, 2013)

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. - Kazunari Enokimoto; Xiaoqing Wen; Kohei Miyase; Jiun-Lang Huang; Seiji Kajihara; Laung-Terng Wang (VLSI Design, 2013)

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. - Yuta Yamato; Kohei Miyase; Seiji Kajihara; Xiaoqing Wen; Laung-Terng Wang; Michael A. Kochte (IEEE Des. Test, 2013)

Testing of Synchronizers in Asynchronous FIFO. - Hyoung-Kook Kim; Laung-Terng Wang; Yu-Liang Wu; Wen-Ben Jone (J. Electron. Test., 2013)

GPU-based timing-aware test generation for small delay defects. - Kuan-Yu Liao; Po-Juei Chen; Ang-Feng Lin; James Chien-Mo Li; Michael S. Hsiao; Laung-Terng Wang (ETS, 2014)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. - Akihiro Tomita; Xiaoqing Wen; Yasuo Sato; Seiji Kajihara; Kohei Miyase; Stefan Holst; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (IEICE Trans. Inf. Syst., 2014)

SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. - Chun-Hao Chang; Kuen-Wei Yeh; Jiun-Lang Huang; Laung-Terng Wang (ATS, 2015)

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. - Kuen-Wei Yeh; Jiun-Lang Huang; Laung-Terng Wang (J. Electron. Test., 2016)

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding. - Dong Xiang; Xiaoqing Wen; Laung-Terng Wang (IEEE Trans. Very Large Scale Integr. Syst., 2017)