A bit serial LDI recursive digital filter. - Laurence E. Turner; Peter B. Denyer; David Renshaw 001 (ICASSP, 1984)

Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms. - R. Nagalla; Laurence E. Turner (VLSI, 1991)

A method of evaluating the effects of signal quantization at arbitrary locations in recursive digital filters. - Stephen Worthington; Laurence E. Turner (ISCAS, 1993)

DSP System Synthesis Including Variable Data Path Width. - Bruce A. Johnston; Peter J. W. Graumann; Laurence E. Turner (ISCAS, 1994)

Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs. - Gopal Panneerselvam; Peter J. W. Graumann; Laurence E. Turner (FPL, 1995)

Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs. - Laurence E. Turner; Peter J. W. Graumann (FPL, 1995)

BIT-Serial FIR Filters with CSD Coefficients for FPGAs. - Laurence E. Turner; Peter J. W. Graumann; S. G. Gibb (FPL, 1995)

An FPGA implementation of a matched filter detector for spread spectrum communications systems. - T. Mathews; S. G. Gibb; Laurence E. Turner; Peter J. W. Graumann; Michel Fattouche (FPL, 1997)

The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. - Trevor W. Fox; Laurence E. Turner (ISCAS (2), 2001)

Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. - Ryan N. Schneider; Laurence E. Turner; Michal M. Okoniewski (FPGA, 2002)

A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM. - Alex Carreira; Trevor W. Fox; Laurence E. Turner (FPL, 2002)

Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. - Trevor W. Fox; Laurence E. Turner (FPL, 2002)

A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. - Alex Carreira; Trevor W. Fox; Laurence E. Turner (FPT, 2002)

Low coefficient complexity approximations of the one dimensional discrete cosine transform. - Trevor W. Fox; Laurence E. Turner (ISCAS (1), 2002)

The Automatic Generation of Application Specific Processors. - S. G. Gibb; Laurence E. Turner (IWLS, 2002)

The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. - Trevor W. Fox; Alex Carreira; Laurence E. Turner (IWSOC, 2003)

A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs. - Alex Carreira; Trevor W. Fox; Laurence E. Turner (EURASIP J. Adv. Signal Process., 2003)

Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations. - Trevor W. Fox; Laurence E. Turner (EURASIP J. Adv. Signal Process., 2003)

Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm. - Sean E. Krakiwsky; Laurence E. Turner; Michal M. Okoniewski (ISCAS (5), 2004)

A Field Programmable Bit-Serial Digital Signal Processor. - S. A. Rahim; Laurence E. Turner (IWSOC, 2004)

Bit-Serial Digital Filter Implementation using a Custom C Compiler. - Dan Cyca; Laurence E. Turner (APCCAS, 2006)

A C compiler for implementing FPGA based bit-serial DSP systems. - Dan Cyca; Laurence E. Turner (FPT, 2006)