Formal Verification of VHDL Descriptions in the Prevail Environment. - Dominique Borrione; Laurence V. Pierre; Ashraf M. Salem (IEEE Des. Test Comput., 1992)

VHDL Description and Formal Verification of Systolic Multipliers. - Laurence Pierre (CHDL, 1993)

Formal Verification of Hardware using LP and Comparison with Nqthm. - Michel Allemand; Felix Nicoli; Laurence Pierre (Applied Informatics, 1994)

Formal verification of behavioral VHDL specifications: a case study. - Felix Nicoli; Laurence Pierre (EURO-DAC, 1994)

An Automatic Generalization Method for the Inductive Proof of Replicated and Parallel Architectures. - Laurence Pierre (TPCD, 1994)

Describing and verifying synchronous circuits with the Boyer-Moore theorem prover. - Laurence Pierre (CHARME, 1995)

Formal Specification of a Reactive System: An Exercise in VHDL, LOTOS and UNITY. - Laurence Pierre (ED&TC, 1996)

Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. - Dominique Borrione; Julia Dushina; Laurence Pierre (SBCCI, 1998)

A compositional model for the functional verification of high-level synthesis results. - Dominique Borrione; Julia Dushina; Laurence V. Pierre (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Induction-Oriented Formal Verification in Symmetric Interconnection Networks. - Eric Gascard; Laurence Pierre (CHARME, 2001)

Mechanical Verification of Hypercube Algorithms. - Eric Gascard; Laurence Pierre (IPDPS, 2002)

Combining ACL2 and a v-calculus Model-Checker to Verify System-Level Designs. - Magali Contensin; Laurence Pierre (MEMOCODE, 2003)

Formal Proof of Applications Distributed in Symmetric Interconnection Networks. - Eric Gascard; Laurence Pierre (Parallel Process. Lett., 2003)

Model-Checking Systems with Unbounded Variables without Abstraction. - Magali Contensin; Laurence Pierre (AMAST, 2004)

A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. - Dominique Borrione; Amr Helmy; Laurence V. Pierre; Julien Schmaltz (NOCS, 2007)

Executable formal specification and validation of NoC communication infrastructures. - Dominique Borrione; Amr Helmy; Laurence Pierre; Julien Schmaltz (SBCCI, 2008)

A Tractable and Fast Method for Monitoring SystemC TLM Specifications. - Laurence Pierre; Luca Ferro (IEEE Trans. Computers, 2008)

High-level symbolic simulation for automatic model extraction. - Florent Ouchet; Dominique Borrione; Katell Morin-Allory; Laurence Pierre (DDECS, 2009)

Complementary Formal Approaches for Dependability Analysis. - Souheib Baarir; Cécile Braunstein; Renaud Clavel; Emmanuelle Encrenaz; Jean-Michel Ilié; Régis Leveugle; Isabelle Mounier; Laurence Pierre; Denis Poitrenaud (DFT, 2009)

ISIS: Runtime verification of TLM platforms. - Luca Ferro; Laurence Pierre (FDL, 2009)

A Formal Approach to the Verification of Networks on Chip. - Dominique Borrione; Amr Helmy; Laurence Pierre; Julien Schmaltz (EURASIP J. Embed. Syst., 2009)

Formal semantics for PSL modeling layer and application to the verification of transactional models. - Luca Ferro; Laurence Pierre (DATE, 2010)

Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing. - Amr Helmy; Laurence Pierre; Axel Jantsch (DDECS, 2010)

Enhancing the assertion-based verification of TLM designs with reentrancy. - Laurence Pierre; Luca Ferro (MEMOCODE, 2010)

A Design Flow for Critical Embedded Systems. - Vincent Lefftz; Jean Bertrand; Hugues Cassé; Christophe Clienti; Philippe Coussy; Laurent Maillet-Contoz; Philippe Mercier; Pierre Moreau; Laurence Pierre; Emmanuel Vaumorin (SIES, 2010)

Dynamic Verification of SystemC Transactional Models. - Laurence Pierre; Luca Ferro (Model-Based Testing for Embedded Systems, 2011)

Improvement of Assertion-Based Verification through the generation of proper test sequences. - Laurence Pierre; Laila Damri (FDL, 2011)

Runtime Verification of Typical Requirements for a Space Critical SoC Platform. - Luca Ferro; Laurence Pierre; Zeineb Bel Hadj Amor; Jérôme Lachaize; Vincent Lefftz (FMICS, 2011)

Towards Robustness Analysis Using PVS. - Renaud Clavel; Laurence Pierre; Régis Leveugle (ITP, 2011)

A formal framework for testing with assertion checkers in mixed-signal simulation. - Laurence Pierre (ICECS, 2012)

A Mixed Verification Strategy Tailored for Networks on Chip. - Georgios Tsiligiannis; Laurence Pierre (NOCS, 2012)

Integrating PSL properties into SystemC transactional modeling - Application to the verification of a modem SoC. - Laurence Pierre; Luca Ferro; Zeineb Bel Hadj Amor; Philippe Bourgon; Jérôme Quévremont (SIES, 2012)

Automatic refinement of requirements for verification throughout the SoC design flow. - Laurence Pierre; Zeineb Bel Hadj Amor (CODES+ISSS, 2013)

On the Effectiveness of Assertion-Based Verification in an Industrial Context. - Laurence Pierre; Fabrice Pancher; Rodolphe Suescun; Jérôme Quévremont (FMICS, 2013)

A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems. - Martial Chabot; Laurence Pierre (ICTSS, 2014)

A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow. - Zeineb Bel Hadj Amor; Laurence Pierre; Dominique Borrione (VLSI-SoC, 2014)

Towards a toolchain for assertion-driven test sequence generation. - Laurence Pierre (FDL, 2015)

Automatic and configurable instrumentation of C programs with temporal assertion checkers. - Martial Chabot; Kévin Mazet; Laurence Pierre (MEMOCODE, 2015)

A requirement driven testing method for multi-disciplinary system design. - Martial Chabot; Laurence Pierre; Alexandre Nabais-Moreno (MoDELS, 2016)

Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements. - Laurence Pierre (ACM Trans. Design Autom. Electr. Syst., 2016)

Assertion-Based Verification for SoC Models and Identification of Key Events. - Laurence Pierre; Martial Chabot (DSD, 2017)

Automated Testing for Cyber-physical Systems: From Scenarios to Executable Tests. - Martial Chabot; Laurence Pierre; Alexandre Nabais-Moreno (FDL, 2018)

Assertion-Based Verification through Binary Instrumentation. - Enzo Brignon; Laurence Pierre (DATE, 2019)

Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions. - Laurence Pierre (Integr., 2021)