An Object-Oriented Framework for the Formal Verification of Processors. - Laurent Arditi; Hélène Collavizza (ECOOP, 1995)

Towards verifying VHDL descriptions of processors. - Laurent Arditi; Hélène Collavizza (EURO-DAC, 1995)

BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions. - Laurent Arditi (FMCAD, 1996)

A semi-formal methodology for the functional validation of an industrial DSP system. - Laurent Arditi; Gaël Clavé (ISCAS, 2000)

Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System. - Laurent Arditi; Hédi Boufaïed; Arnaud Cavanié; Vincent Stehlé (FME, 2001)

Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. - Laurent Arditi; Gérard Berry; Michael Kishinevsky (FMCAD, 2004)