FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration. - Claire Fenouillet-Béranger; Bernard Previtali; Perrine Batude; Fabrice Nemouchi; Mikaël Cassé; Xavier Garros; Lucie Tosti; Nils Rambal; Dominique Lafond; Hugo Dansas; Luca Pasini; Laurent Brunet; et al. (ESSDERC, 2014)

Impact of intermediate BEOL technology on standard cell performances of 3D VLSI. - Melanie Brocard; Guillaume Berhault; Sébastien Thuries; Fabien Clermidy; Perrine Batude; Claire Fenouillet-Béranger; Laurent Brunet; François Andrieu; Fabien Deprat; Joris Lacord; Olivier Rozeau; Gerald Cibrario; et al. (ESSDERC, 2016)

Opportunities brought by sequential 3D CoolCube™ integration. - Maud Vinet; Perrine Batude; Claire Fenouillet-Béranger; Laurent Brunet; Vincent Mazzocchi; Cao-Minh Vincent Lu; Fabien Deprat; Jessy Micout; Bernard Previtali; Paul Besombes; Nils Rambal; François Andrieu; et al. (ESSDERC, 2016)

Recent advances in 3D VLSI integration. - Claire Fenouillet-Béranger; Perrine Batude; Laurent Brunet; Vincent Mazzocchi; Cao-Minh Vincent Lu; Fabien Deprat; Jessy Micout; M.-P. Samson; Bernard Previtali; Paul Besombes; Nils Rambal; François Andrieu; et al. (ICICDT, 2016)

Guidelines for intermediate back end of line (BEOL) for 3D sequential integration. - Claire Fenouillet-Béranger; S. Beaurepaire; Fabien Deprat; Alexandre Ayres De Sousa; Laurent Brunet; Perrine Batude; Olivier Rozeau; François Andrieu; Paul Besombes; M.-P. Samson; Bernard Previtali; F. Nemouchi; et al. (ESSDERC, 2017)

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices. - Jessy Micout; Quentin Rafhay; Xavier Garros; Mikaël Cassé; Jean Coignus; Luca Pasini; Cao-Minh Vincent Lu; Nils Rambal; Claire Fenouillet-Béranger; Laurent Brunet; G. Romano; R. Gassilloud; et al. (ESSDERC, 2017)

Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells. - Melanie Brocard; Benoît Mathieu; Jean-Philippe Colonna; Cristiano Santos; Claire Fenouillet-Béranger; Cao-Minh Vincent Lu; Gerald Cibrario; Laurent Brunet; Perrine Batude; François Andrieu; Sébastien Thuries; Olivier Billoint (ISVLSI, 2017)

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. - François Andrieu; Perrine Batude; Laurent Brunet; Claire Fenouillet-Béranger; Didier Lattard; Sébastien Thuries; Olivier Billoint; Richard Fournel; Maud Vinet (ICICDT, 2018)

Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration. - Tadeu Mota Frutuoso; Jose Lugo-Alvarez; Xavier Garros; Laurent Brunet; Joris Lacord; Louis Gerrer; Mikaël Cassé; Edoardo Catapano; Claire Fenouillet-Béranger; François Andrieu; Fred Gaillard; Philippe Ferrari (IRPS, 2021)

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. - Tadeu Mota Frutuoso; Xavier Garros; Perrine Batude; Laurent Brunet; Joris Lacord; Benoit Sklénard; V. Lapras; Claire Fenouillet-Béranger; M. Ribotta; A. Magalhaes-Lucas; J. Kanyandekwe; R. Kies; et al. (VLSI Technology and Circuits, 2022)

Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications. - Daphnée Bosch; Abygaël Viey; Tadeu Mota Frutuoso; P. Lheritier; C. Licitra; Nada Zerhouni; A. Albouy; Laurent Brunet; A. Magalhaes-Lucas; L. M. B. da Silva; H. Boutry; M. Husien Fahmy Taha Abdelrahman; et al. (VLSI Technology and Circuits, 2024)

First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications. - J. Luge-Alvarez; J. B. David; Alexandre Siligaris; Vincent Puyal; G. Moritz; Tadeu Mota Frutuoso; V. Lapras; Claire Fenouillet-Béranger; Laurent Brunet; P. Vincent; Didier Lattard; Xavier Garros; et al. (VLSI Technology and Circuits, 2024)