Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. - Wissam Hlayhel; Daniel Litaize; Laurent Fesquet; Jacques Henri Collet (IEEE PACT, 1998)

Implementing Snoop-Coherence Protocol for Future SMP Architectures. - Wissam Hlayhel; Jacques Henri Collet; Laurent Fesquet (Euro-Par, 1999)

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SOC, 2001)

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Jerome Quartana (DATE, 2002)

Implementing Asynchronous Circuits on LUT Based FPGAs. - Quoc Thai Ho; Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Robin Rolland (FPL, 2002)

Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. - Anh Vu Dihn Duc; Laurent Fesquet; Marc Renaudin (IWLS, 2002)

Low-Power Asynchronous A/D Conversion. - Emmanuel Allier; Laurent Fesquet; Marc Renaudin; Gilles Sicard (PATMOS, 2002)

Dynamic Voltage Scheduling for Real Time Asynchronous Systems. - Mohammed Es Salhiene; Laurent Fesquet; Marc Renaudin (PATMOS, 2002)

A New Class of Asynchronous A/D Converters Based on Time Quantization. - Emmanuel Allier; Gilles Sicard; Laurent Fesquet; Marc Renaudin (ASYNC, 2003)

Asynchronous FIR Filters: Towards a New Digital Processing Chain. - F. Aeschlimann; Emmanuel Allier; Laurent Fesquet; Marc Renaudin (ASYNC, 2004)

La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. - Laurent Fesquet; Mohammed Es Salhiene; Marc Renaudin (Ann. des Télécommunications, 2004)

FPGA Architecture for Multi-Style Asynchronous Logic. - N. Huot; H. Dubreuil; Laurent Fesquet; Marc Renaudin (DATE, 2005)

PSL-based online monitoring of digital systems. - D. Borionne; M. Liu; P. Ostier; Laurent Fesquet (FDL, 2005)

A Programmable Logic Architecture for Prototyping Clockless Circuits. - Laurent Fesquet; Marc Renaudin (FPL, 2005)

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. - Jerome Quartana; Salim Renane; Arnaud Baixas; Laurent Fesquet; Marc Renaudin (FPL, 2005)

Asynchronous Systems on Programmable Logic. - Laurent Fesquet; Jerome Quartana; Marc Renaudin (ReCoSoC, 2005)

Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. - Bertrand Folco; Vivian Brégier; Laurent Fesquet; Marc Renaudin (VLSI-SoC, 2005)

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. - Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SoC, 2005)

Spectral analysis of a signal driven sampling scheme. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (EUSIPCO, 2006)

Asynchronous Assertion Monitors for multi-Clock Domain System Verification. - Katell Morin-Allory; Laurent Fesquet; Dominique Borrione (IEEE International Workshop on Rapid System Prototyping, 2006)

State-holding in Look-Up Tables: application to asynchronous logic. - Laurent Fesquet; Bertrand Folco; Mathieu Steiner; Marc Renaudin (VLSI-SoC, 2006)

Computationally efficient adaptive rate sampling and filtering. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (EUSIPCO, 2007)

Asynchronous online-monitoring of logical and temporal assertions. - Katell Morin-Allory; Laurent Fesquet; Benjamin Roustan; Dominique Borrione (FDL, 2007)

A Novel Asynchronous e-FPGA Architecture for Security Applications. - Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin; Sumanta Chaudhuri; Sylvain Guilley; Jean-Luc Danger; Philippe Hoogvorst (FPT, 2007)

Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (ICASSP (3), 2007)

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. - Philippe Hoogvorst; Sylvain Guilley; Sumanta Chaudhuri; Alin Razafindraibe; Taha Beyrouthy; Laurent Fesquet (ReCoSoC, 2007)

Physical Design of FPGA Interconnect to Prevent Information Leakage. - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (ARC, 2008)

High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. - Jérémie Hamon; Laurent Fesquet; Benoit Miscopein; Marc Renaudin (ASYNC, 2008)

A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks - Philippe Hoogvorst; Sylvain Guilley; Sumanta Chaudhuri; Jean-Luc Danger; Taha Beyrouthy; Laurent Fesquet (CoRR, 2008)

An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (J. Electr. Comput. Eng., 2008)

Controlling energy and process variability in System-on-Chips: needs for control theory. - Laurent Fesquet; Hatem M. Zakaria (CCA/ISIC, 2009)

Programmable/Stoppable Oscillator Based on Self-Timed Rings. - Eslam Yahya; Oussama Elissati; Hatem M. Zakaria; Laurent Fesquet; Marc Renaudin (ASYNC, 2009)

RAT-based formal verification of QDI asynchronous controllers. - Khaled Alsayeg; Katell Morin-Allory; Laurent Fesquet (FDL, 2009)

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. - Sylvain Guilley; Sumanta Chaudhuri; Laurent Sauvage; Jean-Luc Danger; Taha Beyrouthy; Laurent Fesquet (ICECS, 2009)

Asynchronous design: A promising paradigm for electronic circuits and systems. - Eslam Yahya; Laurent Fesquet (ICECS, 2009)

Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (EURASIP J. Adv. Signal Process., 2009)

Constrained Asynchronous Ring Structures for Robust Digital Oscillators. - Jérémie Hamon; Laurent Fesquet; Benoit Miscopein; Marc Renaudin (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Delay Insensitivity Does Not Mean Slope Insensitivity! - Florent Ouchet; Katell Morin-Allory; Laurent Fesquet (ASYNC, 2010)

Synthesis of asynchronous monitors for critical electronic systems. - Alexandre Porcher; Katell Morin-Allory; Laurent Fesquet (DDECS, 2010)

Targeting ultra-low power consumption with non-uniform sampling and filtering. - Laurent Fesquet; Gilles Sicard; Brigitte Bidégaray-Fesquet (ISCAS, 2010)

Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. - Oussama Elissati; Eslam Yahya; Sébastien Rieubon; Laurent Fesquet (PATMOS, 2010)

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. - Oussama Elissati; Sébastien Rieubon; Eslam Yahya; Laurent Fesquet (VLSI-SoC (Selected Papers), 2010)

A high-speed high-resolution low-phase noise oscillator using self-timed rings. - Oussama Elissati; Eslam Yahya; Sébastien Rieubon; Laurent Fesquet (VLSI-SoC, 2010)

IIR digital filtering of non-uniformly sampled signals via state representation. - Laurent Fesquet; Brigitte Bidégaray-Fesquet (Signal Process., 2010)

Formal Verification of C-element Circuits. - Chao Yan 001; Florent Ouchet; Laurent Fesquet; Katell Morin-Allory (ASYNC, 2011)

Does asynchronous technology bring robustness in synchronous circuit monitoring? - Alexandre Porcher; Katell Morin-Allory; Laurent Fesquet; Alejandro Chagoya (FDL, 2011)

C-elements for Hardened Self-timed Circuits. - Florent Ouchet; Katell Morin-Allory; Laurent Fesquet (PATMOS, 2011)

An event-driven FIR filter: Design and implementation. - Taha Beyrouthy; Laurent Fesquet (International Symposium on Rapid System Prototyping, 2011)

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (CoRR, 2011)

Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs. - Hatem M. Zakaria; Laurent Fesquet (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. - Abdelkarim Cherkaoui; Viktor Fischer; Alain Aubert; Laurent Fesquet (DATE, 2012)

New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school. - Evelyne Excoffon; Francine Papillon; Laurent Fesquet; Ahmad Bsiesy; Olivier Bonnaud (ITHET, 2012)

Empirical Recovery of Input Nonlinearity in Distributed Element Models. - Przemyslaw Sliwinski; Krzysztof S. Berezowski; Pawel Wachel; Gilles Sicard; Laurent Fesquet (ALCOSP, 2013)

A Self-Timed Ring Based True Random Number Generator. - Abdelkarim Cherkaoui; Viktor Fischer; Alain Aubert; Laurent Fesquet (ASYNC, 2013)

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. - Eslam Yahya; Laurent Fesquet; Yehea I. Ismail; Marc Renaudin (ASYNC, 2013)

A Very High Speed True Random Number Generator with Entropy Assessment. - Abdelkarim Cherkaoui; Viktor Fischer; Laurent Fesquet; Alain Aubert (CHES, 2013)

Innovating projects as a pedagogical strategy for the French network for education in microélectronics and nanotechnologies. - Olivier Bonnaud; Laurent Fesquet (MSE, 2013)

An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications. - Taha Beyrouthy; Laurent Fesquet (Int. J. Reconfigurable Comput., 2013)

Low data rate architecture for smart image sensor. - Amani Darwish; Gilles Sicard; Laurent Fesquet (IMSE, 2014)

Trends in nanoelectronic education from FDSOI and FinFET technologies to circuit design specifications. - Olivier Bonnaud; Laurent Fesquet (EWME, 2014)

Distributed asynchronous controllers for clock management in low power systems. - Chadi Al Khatib; Claire Aupetit; Alejandro Chagoya; Cyril Chevalier; Gilles Sicard; Laurent Fesquet (ICECS, 2014)

FINMINA: A French national project to promote innovation in higher education in microelectronics and nanotechnologies. - Olivier Bonnaud; Pascal Nouet; Laurent Fesquet; Taieb Mohammed-Brahim (ITHET, 2014)

1-Level crossing sampling scheme for low data rate image sensors. - Amani Darwish; Laurent Fesquet; Gilles Sicard (NEWCAS, 2014)

Self-timed rings as low-phase noise programmable oscillators. - Laurent Fesquet; Abdelkarim Cherkaoui; Oussama Elissati (NEWCAS, 2014)

Designing ultra-low power systems with non-uniform sampling and event-driven logic. - Giuseppe Roa; Tugdual Le Pelleter; Agnès Bonvilain; Alejandro Chagoya; Laurent Fesquet (SBCCI, 2014)

Adaptive rate filtering a computationally efficient signal processing approach. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (Signal Process., 2014)

A method to automatically determine the level-crossing thresholds in non-uniform sampling and processing. - Cansu Arslan; Julien Poujaud; Laurent Fesquet (EBCCSP, 2015)

Data sampling and processing: Uniform vs. non-uniform schemes. - Taha Beyrouthy; Laurent Fesquet; Robin Rolland (EBCCSP, 2015)

RTL simulation of an asynchronous reading architecture for an event-driven image sensor. - Amani Darwish; Laurent Fesquet; Gilles Sicard (EBCCSP, 2015)

Communicating and smart objects: Multidisciplinary topics for the innovative education in microelectronics and its applications. - Olivier Bonnaud; Laurent Fesquet (ITHET, 2015)

Towards multidisciplinarity for microelectronics education: A strategy of the French national network. - Olivier Bonnaud; Laurent Fesquet (MSE, 2015)

A generic clock controller for low power systems: Experimentation on an AXI bus. - Chadi Al Khatib; Claire Aupetit; Cyril Chevalier; Chouki Aktouf; Gilles Sicard; Laurent Fesquet (VLSI-SoC, 2015)

Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology. - Otto Aureliano Rolloff; Rodrigo Possamai Bastos; Laurent Fesquet (Microelectron. Reliab., 2015)

Simple tri-state logic Trojans able to upset properties of ring oscillators. - Leonel Acunha Guimaraes; Rodrigo Possamai Bastos; Thiago Ferreira de Paiva Leite; Laurent Fesquet (DTIS, 2016)

Asynchronous implementation of an event-driven adaptive FIR filter. - Taha Beyrouthy; Ahmed Roshdy; Mohammad Salman; Saeed Mian Qaisar; Laurent Fesquet (EBCCSP, 2016)

Levels, peaks, slopes... which sampling for which purpose? - Brigitte Bidégaray-Fesquet; Laurent Fesquet (EBCCSP, 2016)

High-level synthesis for event-based systems. - Jean Simatic; Rodrigo Possamai Bastos; Laurent Fesquet (EBCCSP, 2016)

Delay partitioning helps reducing variability in 3DVLSI. - A. Ayres; Olivier Rozeau; B. Borot; Laurent Fesquet; Maud Vinet (ESSCIRC, 2016)

Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network. - Olivier Bonnaud; Laurent Fesquet (EWME, 2016)

MOOC and practices in electrical and information engineering: Complementary approaches. - Olivier Bonnaud; Laurent Fesquet (ITHET, 2016)

Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits. - Thiago Ferreira de Paiva Leite; Rodrigo Possamai Bastos; Rodrigo Iga Jadue; Laurent Fesquet (PATMOS, 2016)

New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. - Jean Simatic; Abdelkarim Cherkaoui; Rodrigo Possamai Bastos; Laurent Fesquet (SBCCI, 2016)

A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. - Jean Simatic; Abdelkarim Cherkaoui; François Bertrand; Rodrigo Possamai Bastos; Laurent Fesquet (ASYNC, 2017)

Event-driven image sensor application: Event-driven image segmentation. - Amani Darwish; Hassan Abbass; Laurent Fesquet; Gilles Sicard (EBCCSP, 2017)

Event-based design strategy for circuit electromagnetic compatibility. - Sophie Germain; Sylvain Engels; Laurent Fesquet (EBCCSP, 2017)

High-level synthesis of an event-driven windowing process. - Saeed Mian Qaisar; Jean Simatic; Laurent Fesquet (EBCCSP, 2017)

Towards consistency checking between HDL and UPF descriptions. - Arthur Kalsing; Laurent Fesquet; Chouki Aktouf (FDL, 2017)

A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. - Arthur Kalsing; Laurent Fesquet; Chouki Aktouf (FDL (Selected Papers), 2017)

CAR: On the highway towards de-synchronization. - François Bertrand; Abdelkarim Cherkaoui; Jean Simatic; Anthony Maure; Laurent Fesquet (ICECS, 2017)

A Bayesian Stochastic Machine for Sound Source Localization. - Raphael Frisch; Raphaël Laurent; Marvin Faix; Laurent Girin; Laurent Fesquet; Augustin Lux; Jacques Droulez; Pierre Bessière; Emmanuel Mazer (ICRC, 2017)

Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. - Ali Skaf; Jean Simatic; Laurent Fesquet (ISCAS, 2017)

Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors. - Leonel Acunha Guimaraes; Rodrigo Possamai Bastos; Laurent Fesquet (ISVLSI, 2017)

Self-timed Ring based True Random Number Generator: Threat model and countermeasures. - Gregoire Gimenez; Abdelkarim Cherkaoui; Raphael Frisch; Laurent Fesquet (IVSW, 2017)

Innovative practice in the French microelectronics education targeting the industrial needs. - Olivier Bonnaud; Laurent Fesquet (MSE, 2017)

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. - Assia El-Hadbi; Abdelkarim Cherkaoui; Oussama Elissati; Jean Simatic; Laurent Fesquet (NEWCAS, 2017)

A Cognitive Stochastic Machine Based on Bayesian Inference: A Behavioral Analysis. - Raphael Frisch; Marvin Faix; Emmanuel Mazer; Laurent Fesquet; Augustin Lux (ICCI*CC, 2018)

A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. - Sophie Germain; Sylvain Engels; Laurent Fesquet (ASYNC, 2018)

Static Timing Analysis of Asynchronous Bundled-Data Circuits. - Gregoire Gimenez; Abdelkarim Cherkaoui; Guillaume Cogniard; Laurent Fesquet (ASYNC, 2018)

Subthreshold logic for low-area and energy efficient true random number generator. - Mathieu Coustans; Abdelkarim Cherkaoui; Laurent Fesquet; Christian Terrier; Stephanie Salgado; Thomas Eberhardt; Maher Kayal (COOL CHIPS, 2018)

Non-intrusive testing technique for detection of Trojans in asynchronous circuits. - Leonel Acunha Guimaraes; Thiago Ferreira de Paiva Leite; Rodrigo Possamai Bastos; Laurent Fesquet (DATE, 2018)

Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. - Oussama Elissati; Assia El-Hadbi; Abdelkarim Cherkaoui; Sébastien Rieubon; Laurent Fesquet (DCIS, 2018)

An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems. - Timothe Turko; Wilfried Uhring; Foudil Dadouche; Laurent Fesquet (ICECS, 2018)

Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. - Alexis Rodrigo Iga Jadue; Rodrigo Possamai Bastos; Thiago Ferreira de Paiva Leite; Otto Aureliano Rolloff; M. Diallo; Laurent Fesquet (ISCAS, 2018)

Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society. - Olivier Bonnaud; Laurent Fesquet; Luc Hébrard (LASCAS, 2018)

Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits. - Rodrigo Possamai Bastos; Leonel Acunha Guimaraes; Frank Sill Torres; Laurent Fesquet (Microelectron. J., 2018)

A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems. - Thiago Ferreira de Paiva Leite; Laurent Fesquet; Rodrigo Possamai Bastos (Microelectron. Reliab., 2018)

From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. - Grégoire Gimenez; Jean Simatic; Laurent Fesquet (ASYNC, 2019)

On-Line Adjustable Precision Computing. - Ali Skaf; Mona Ezzadeen; Mounir Benabdenbi; Laurent Fesquet (DTIS, 2019)

A new synthesis approach for non-uniform filters in the log-scale: Proof of concept. - Brigitte Bidégaray-Fesquet; Laurent Fesquet (EBCCSP, 2019)

Comparison of Synchronous and Asynchronous FIR Filter Architectures. - Yoan Decoudu; Jean Simatic; Pauline Alexandre; Katell Morin-Allory; Laurent Fesquet (EBCCSP, 2019)

Time-to-Digital Converters: A Literature Review and New Perspectives. - Assia El-Hadbi; Oussama Elissati; Laurent Fesquet (EBCCSP, 2019)

An Event-Based Strategy for ASK demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (EBCCSP, 2019)

Skilled manpower shortage in microelectronics: a challenge for the French education microelectronics network. - Olivier Bonnaud; Laurent Fesquet; Ahmad Bsiesy (ITHET, 2019)

A Distributed Body-Biasing Strategy for Asynchronous Circuits. - Laurent Fesquet; Yoan Decoudu; Alexis Rodrigo Iga Jadue; Thiago Ferreira de Paiva Leite; Otto Aureliano Rolloff; M. Diallo; Rodrigo Possamai Bastos; Katell Morin-Allory; Sylvain Engels (VLSI-SoC, 2019)

A Digital Event-Based Strategy for ASK demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (VLSI-SoC, 2019)

A Self-Timed Ring based PUF. - Grégoire Gimenez; Abdelkarim Cherkaoui; Laurent Fesquet (ASYNC, 2020)

Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression. - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (EBCCSP, 2020)

An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection. - Saeed Mian Qaisar; Laurent Fesquet (EBCCSP, 2020)

At-speed DfT Architecture for Bundled-data Design. - Ricardo Aquino Guazzelli; Laurent Fesquet (ITC, 2020)

A Novel Event Based Image Sensor with spacial and temporal redundancy suppression. - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (NEWCAS, 2020)

Improved $ pi$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver. - Ali Al Shakoush; Estelle Lauga-Larroze; Florence Podevin; Sana Ibrahim; Laurent Fesquet; Sylvain Bourdel (NEWCAS, 2020)

From High-Level Synthesis to Bundled-Data Circuits. - Yoan Decoudu; Jean Simatic; Katell Morin-Allory; Laurent Fesquet (SAMOS, 2020)

Trojan Detection Test for Clockless Circuits. - Ricardo Aquino Guazzelli; Matheus Garay Trindade; Leonel Acunha Guimaraes; Thiago Ferreira de Paiva Leite; Laurent Fesquet; Rodrigo Possamai Bastos (J. Electron. Test., 2020)

An asynchronous hybrid pixel image sensor. - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (ASYNC, 2021)

Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (EBCCSP, 2021)

Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35μ m CMOS Proof-of-Concept Prototype. - Assia El-Hadbi; Oussama Elissati; Laurent Fesquet (I2MTC, 2021)

A hybrid event-based pixel for low-power image sensing. - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (ICECS, 2021)

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. - Jérémy Belot; Abdelkarim Cherkaoui; Raphaël Laurent; Laurent Fesquet (ICECS, 2021)

A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. - Yoan Decoudu; Katell Morin-Allory; Laurent Fesquet (VLSI-SoC, 2021)

An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. - Jérémy Belot; Abdelkarim Cherkaoui; Raphaël Laurent; Laurent Fesquet (IEEE Des. Test, 2021)

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout. - Enagnon Aguénounon; Safa Razavinejad; Jean-Baptiste Schell; Mohammadreza Dolatpoor Lakeh; Wassim Khaddour; Foudil Dadouche; Jean-Baptiste Kammerer; Laurent Fesquet; Wilfried Uhring (Sensors, 2021)

An improved event-by-event clustering algorithm for noisy acquisition. - Xavier Lesage; Rosalie Tran; Stéphane Mancini; Laurent Fesquet (EBCCSP, 2022)

A Novel Event-Based Method for ASK Demodulation. - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (LASCAS, 2022)

Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis. - Hasan Moussa; Sana Ibrahim; Estelle Lauga-Larroze; Florence Podevin; Sylvain Bourdel; Laurent Fesquet (NEWCAS, 2022)

N-Path Mixer with Wide Rejection Including the 7th Harmonic for Low Power Multi-standard Receivers. - Ali Al Shakoush; Sana Ibrahim; Serge Subias; Florence Podevin; Manuel J. Barragán; Dayana A. Pino-Monroy; Imadeddine Bendjeddou; Estelle Lauga-Larroze; Laurent Fesquet; Thierry Taris; Sylvain Bourdel (NEWCAS, 2022)

Low-Throughput Event-Based Image Sensors and Processing. - Laurent Fesquet; Rosalie Tran; Xavier Lesage; Mohamed Akrarai; Stéphane Mancini; Gilles Sicard (DATE, 2023)

Making Digital N-Path Mixers. - Hasan Moussa; Jessica Gonsalves; Estelle Lauga-Larroze; Sana Ibrahim; Florence Podevin; Sylvain Bourdel; Laurent Fesquet (DCIS, 2023)

A Generic CDC Modeling for Data Stability Verification. - Diana Kalel; Jean-Christophe Brignone; Laurent Fesquet; Katell Morin-Allory (ICECS, 2023)

Method for Data-Driven Pruning in Micropipeline Circuits. - Cristiano Merio; Xavier Lesage; Ali Naimi; Sylvain Engels; Katell Morin-Allory; Laurent Fesquet (VLSI-SoC, 2023)

Velocity and Color Estimation Using Event-Based Clustering. - Xavier Lesage; Rosalie Tran; Stéphane Mancini; Laurent Fesquet (Sensors, 2023)

Data-driven Processing Element for Sparse Convolutional Neural Networks. - Xavier Lesage; Cristiano Merio; Fernando Welzel; Luca Sauer de Araujo; Sylvain Engels; Laurent Fesquet (NewCAS, 2024)

Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation. - Assia El-Hadbi; Oussama Elissati; Laurent Fesquet (VLSI-SoC, 2024)

A New Control Law for N-Path Mixer Switches Enhancing Harmonic Rejection. - Hasan Moussa; Estelle Lauga-Larroze; Laurent Fesquet (VLSI-SoC, 2024)

Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic. - Sana Ibrahim; Ali Al Shakoush; Serge Subias; Loic Vincent; Manuel J. Barragan Asian; Laurent Fesquet; Florence Podevin; Sylvain Bourdel (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. - Claire Fenouillet-Béranger; Laurent Fesquet; Rihab Chouk; Gabriel Pares; Baudoin Martineau; Marie Claire Cyrille; Thierry Poiroux; Olivier Billoint; Dominique Noguet (DDECS, 2025)

TIMA-PUF: Time Measurement Based Arbiter PUF. - Azzadine Thajte; Laurent Fesquet; Giorgio Di Natale (IOLTS, 2025)

Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits. - Jéssica Gonsalves Santos; Ismael de Almeida Junior; Sylvain Engels; Robin Wilson; Laurent Fesquet (SBCCI, 2025)