A Customizable Neural Processor for Distributed Neural Network. - J. Quali; Gabriele Saucier; P. Y. Alla; Jacques Trilhe; Laurent Masse-Navette (VLSI, 1991)

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. - Subhendu Roy; David Z. Pan; Pavlos M. Mattheakis; Peter S. Colyer; Laurent Masse-Navette; Pierre-Olivier Ribet (ACM Great Lakes Symposium on VLSI, 2015)

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. - Subhendu Roy; Pavlos M. Mattheakis; Laurent Masse-Navette; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (DAC, 2017)

Timing-Driven and Placement-Aware Multibit Register Composition. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)