Silicon-level Solutions to Counteract Passive and Active Attacks. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Nidhal Selmane; Renaud Pacalet (FDTC, 2008)

Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Philippe Hoogvorst (FPL, 2008)

Place-and-Route Impact on the Security of DPL Designs in FPGAs. - Sylvain Guilley; Sumanta Chaudhuri; Jean-Luc Danger; Laurent Sauvage; Philippe Hoogvorst; Maxime Nassar; Tarik Graba; Vinh-Nga Vong (HOST, 2008)

Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Tarik Graba; Yves Mathieu (SSIRI, 2008)

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. - Sylvain Guilley; Laurent Sauvage; Philippe Hoogvorst; Renaud Pacalet; Guido Marco Bertoni; Sumanta Chaudhuri (IEEE Trans. Computers, 2008)

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. - Laurent Sauvage; Sylvain Guilley; Jean-Luc Danger; Yves Mathieu; Maxime Nassar (DATE, 2009)

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. - Sylvain Guilley; Sumanta Chaudhuri; Laurent Sauvage; Jean-Luc Danger; Taha Beyrouthy; Laurent Fesquet (ICECS, 2009)

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. - Shivam Bhasin; Jean-Luc Danger; Florent Flament; Tarik Graba; Sylvain Guilley; Yves Mathieu; Maxime Nassar; Laurent Sauvage; Nidhal Selmane (ReConFig, 2009)

DPL on Stratix II FPGA: What to Expect?. - Laurent Sauvage; Maxime Nassar; Sylvain Guilley; Florent Flament; Jean-Luc Danger; Yves Mathieu (ReConFig, 2009)

Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. - Laurent Sauvage; Sylvain Guilley; Yves Mathieu (ACM Trans. Reconfigurable Technol. Syst., 2009)

Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. - Shivam Bhasin; Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger (CT-RSA, 2010)

Far Correlation-based EMA with a precharacterized leakage model. - Olivier Meynard; Sylvain Guilley; Jean-Luc Danger; Laurent Sauvage (DATE, 2010)

Fault Injection Resilience. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Nidhal Selmane (FDTC, 2010)

Defeating Any Secret Cryptography with SCARE Attacks. - Sylvain Guilley; Laurent Sauvage; Julien Micolod; Denis Réal; Frédéric Valette (LATINCRYPT, 2010)

Cross-Correlation Cartography. - Laurent Sauvage; Sylvain Guilley; Florent Flament; Jean-Luc Danger; Yves Mathieu (ReConFig, 2010)

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. - Laurent Sauvage; Maxime Nassar; Sylvain Guilley; Florent Flament; Jean-Luc Danger; Yves Mathieu (Int. J. Reconfigurable Comput., 2010)

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics. - Sylvain Guilley; Laurent Sauvage; Florent Flament; Vinh-Nga Vong; Philippe Hoogvorst; Renaud Pacalet (IEEE Trans. Computers, 2010)

Performance evaluation of protocols resilient to physical attacks. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Nidhal Selmane; Denis Réal (HOST, 2011)

A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. - Taoufik Chouta; Jean-Luc Danger; Laurent Sauvage; Tarik Graba (DSD, 2012)

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. - Laurent Sauvage; Sylvain Guilley; Florent Flament; Jean-Luc Danger; Yves Mathieu (Int. J. Reconfigurable Comput., 2012)

A Pre-processing Composition for Secret Key Recovery on Android Smartphone. - Yuto Nakano; Youssef Souissi; Robert Nguyen; Laurent Sauvage; Jean-Luc Danger; Sylvain Guilley; Shinsaku Kiyomoto; Yutaka Miyake (WISTP, 2014)

Hardware Trojan Horses in Cryptographic IP Cores. - Shivam Bhasin; Jean-Luc Danger; Sylvain Guilley; Xuan Thuy Ngo; Laurent Sauvage (IACR Cryptol. ePrint Arch., 2014)

Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest. - Christophe Clavier; Jean-Luc Danger; Guillaume Duc; M. Abdelaziz Elaabid; Benoît Gérard; Sylvain Guilley; Annelie Heuser; Michael Kasper; Yang Li 001; Victor Lomné; Daisuke Nakatsu; Kazuo Ohta; et al. (J. Cryptogr. Eng., 2014)

High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. - Lionel Rivière; Zakaria Najm; Pablo Rauzy; Jean-Luc Danger; Julien Bringer; Laurent Sauvage (IACR Cryptol. ePrint Arch., 2015)

Differential Fault Analysis on Midori. - Wei Cheng 003; Yongbin Zhou; Laurent Sauvage (ICICS, 2016)

Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology. - Kazuhide Fukushima; Youssef Souissi; Seira Hidano; Robert Nguyen; Jean-Luc Danger; Sylvain Guilley; Yuto Nakano; Shinsaku Kiyomoto; Laurent Sauvage (Trustcom/BigDataSE/ISPA, 2016)

How Far Can We Reach? Breaking RSM-Masked AES-128 Implementation Using Only One Trace. - Wei Cheng 003; Chao Zheng; Yuchen Cao; Yongbin Zhou; Hailong Zhang 001; Sylvain Guilley; Laurent Sauvage (IACR Cryptol. ePrint Arch., 2017)

Multi-level formal verification - A new approach against fault injection attack. - Laurent Sauvage; Tarik Graba; Thibault Porteboeuf (J. Cryptogr. Eng., 2017)

Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification. - Sofiane Takarabt; Kais Chibani; Adrien Facon; Sylvain Guilley; Yves Mathieu; Laurent Sauvage; Youssef Souissi (IVSW, 2018)

Cache-Timing Attacks Still Threaten IoT Devices. - Sofiane Takarabt; Alexander Schaub 001; Adrien Facon; Sylvain Guilley; Laurent Sauvage; Youssef Souissi; Yves Mathieu (C2SI, 2019)

Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer. - Oualid Trabelsi; Laurent Sauvage; Jean-Luc Danger (AsianHOST, 2020)

Formal Evaluation and Construction of Glitch-resistant Masked Functions. - Sofiane Takarabt; Sylvain Guilley; Youssef Souissi; Khaled Karray; Laurent Sauvage; Yves Mathieu (HOST, 2021)

Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. - Roukoz Nabhan; Jean-Max Dutertre; Jean-Baptiste Rigaud; Jean-Luc Danger; Laurent Sauvage (DATE, 2023)

A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models. - Roukoz Nabhan; Jean-Max Dutertre; Jean-Baptiste Rigaud; Jean-Luc Danger; Laurent Sauvage (FDTC, 2023)

High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSA. - Arnaud Varillon; Laurent Sauvage; Jean-Luc Danger (SPACE, 2023)

Investigating Efficient Deep Learning Architectures For Side-Channel Attacks on AES. - Yohaï-Eliel Berreby; Laurent Sauvage (CoRR, 2023)

Quasi-linear Masking to Protect Kyber against both SCA and FIA. - Pierre-Augustin Berthet; Cédric Tavernier; Jean-Luc Danger; Laurent Sauvage (IACR Cryptol. ePrint Arch., 2023)

EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design. - Roukoz Nabhan; Jean-Max Dutertre; Jean-Baptiste Rigaud; Jean-Luc Danger; Laurent Sauvage (IOLTS, 2024)

Masked Vector Sampling for HQC. - Maxime Spyropoulos; David Vigilant; Fabrice Perion; Renaud Pacalet; Laurent Sauvage (IACR Cryptol. ePrint Arch., 2024)

Side-Channel Sensitivity Analysis on HQC: Towards a Fully Masked Implementation. - Guillaume Goy; Maxime Spyropoulos; Nicolas Aragon; Philippe Gaborit; Renaud Pacalet; Fabrice Perion; Laurent Sauvage; David Vigilant (IACR Cryptol. ePrint Arch., 2025)