A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (ETS, 2010)

On using a SPICE-like TSTAC™ eFlash model for design and test. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (DDECS, 2011)

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (J. Electron. Test., 2012)

High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology. - Piyush Jain; Akshay Kumar; Nicolaas Van Winkelhoff; Didier Gayraud; Surya Gupta; Abdelali El Amraoui; Giorgio Palma; Alexandra Gourio; Laurent Vachez; Luc Palau; Jean-Christophe Buy; Cyrille Dray (DATE, 2020)