A single-chip CMOS UHF RFID Reader transceiver for mobile applications. - Le Ye; Huailin Liao; Fei Song; Jiang Chen; Congyin Shi; Chen Li 014; Junhua Liu; Ru Huang 001; Jinshu Zhao; Huiling Xiao; Ruiqiang Liu; Xinan Wang (ESSCIRC, 2009)

A 17-tap 3.5 Gbps finite impulse response pulse shaping filter for 60 GHz transmitter with QPSK modulation. - Jinshu Zhao; Marcus Hellfeld; Thomas Wolf; Frank Ellinger; Le Ye (ESSCIRC, 2010)

A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications. - Le Ye; Huailin Liao; Fei Song; Jiang Chen; Chen Li 014; Jinshu Zhao; Ruiqiang Liu; Chuan Wang; Congyin Shi; Junhua Liu; Ru Huang 001; Yangyuan Wang (IEEE J. Solid State Circuits, 2010)

-99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver. - Congyin Shi; Chuan Wang; Le Ye; Huailin Liao (ISCAS, 2011)

A 0.47mW 6th-order 20MHz active filter using highly power-efficient Opamp. - Le Ye; Congyin Shi; Huailin Liao; Ru Huang 001 (ISCAS, 2011)

A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique. - Long Chen 009; Chuan Wang; Chen Li 014; Le Ye; Huailin Liao; Ru Huang 001 (ISCAS, 2012)

Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads. - Yixiao Wang; Le Ye; Huailin Liao; Ru Huang 001 (ISCAS, 2012)

Widely reconfigurable 8th-order chebyshev analog baseband IC with proposed push-pull op-amp for Software-Defined Radio in 65nm CMOS. - Le Ye; Yixiao Wang; Long Chen 009; Huailin Liao; Ru Huang 001 (ISCAS, 2012)

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter. - Yongan Zheng; Le Ye; Long Chen 009; Huailin Liao; Ru Huang 001 (ISCAS, 2013)

A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process. - Junhua Liu; Chen Li 014; Long Chen 009; Congyin Shi; Xuankai Weng; Yixiao Wang; Jiayi Wang; Yu Liao; Le Ye; Huailin Liao; Ru Huang 001 (Sci. China Inf. Sci., 2013)

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps. - Le Ye; Congyin Shi; Huailin Liao; Ru Huang 001; Yangyuan Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A UHF RFID reader transmitter with digital CMOS power amplifier. - Ying Guo; Long Chen 009; Tao Xia; Le Ye; Xing Zhang 002; Huailin Liao (ISCAS, 2014)

A 4.2 mm2 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS. - Long Chen 009; Yixiao Wang; Chuan Wang; Jiayi Wang; Congyin Shi; Xuankai Weng; Le Ye; Junhua Liu; Huailin Liao; Yangyuan Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS. - Yixiao Wang; Le Ye; Huailin Liao; Ru Huang 001; Yangyuan Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Benchmarking TFET from a circuit level perspective: Applications and guideline. - Lingyi Guo; Le Ye; Cheng Chen; Qianqian Huang; Libo Yang; Zhu Lv; Xia An; Ru Huang 001 (ISCAS, 2017)

A tunable transformer-based CMOS directional coupler for UHF RFID readers. - Yongan Zheng; Le Ye; Xiucheng Hao; Ying Guo; Runhua Wang; Huailin Liao (IEICE Electron. Express, 2017)

Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications. - Libo Yang; Jiadi Zhu; Cheng Chen; Zhixuan Wang; Zexue Liu; Qianqian Huang; Le Ye; Ru Huang 001 (ISCAS, 2018)

Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance. - Zhixuan Wang; Yuan Zhong; Cheng Chen; Le Ye; Qianqian Huang; Libo Yang; Yangyuan Wang; Ru Huang 001 (ISCAS, 2019)

A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection. - Xiaolong Chen; Enbin Gong; Hao Zhang 119; Le Ye; Ru Huang 001 (ISCAS, 2020)

2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT. - Enbin Gong; Hao Zhang 119; Xiaolong Chen; Le Ye; Ru Huang 001 (ISCAS, 2020)

20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. - Zhixuan Wang; Le Ye; Hao Zhanq; Jiayoon Ru; Haitao Fan; Yangyuan Wang; Ru Huang 001 (ISSCC, 2020)

Challenges and Solutions of the TFET Circuit Design. - Zhiting Lin; Panpan Chen; Le Ye; Xu Yan; Lanzhi Dong; Shuguang Zhang; Zhou Yang 009; Chunyu Peng; Xiulong Wu; Junning Chen (IEEE Trans. Circuits Syst., 2020)

A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter Amplifiers. - Yibo Zhao 003; Huajun Zhang 001; Yaopeng Hu; Yuanxin Bao; Le Ye; Wanyuan Qu; Menglian Zhao; Zhichao Tan (CICC, 2021)

SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. - Yufei Ma 002; Gokul Krishnan; Yu Cao 001; Le Ye; Ru Huang 001 (FPGA, 2021)

5.1 A 1.5μW 0.135pJ·%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. - Heyi Li; Zhichao Tan; Yuanxin Bao; Han Xiao 006; Hao Zhang 119; Kaixuan Du; Yihan Zhang 002; Le Ye; Ru Huang 001 (ISSCC, 2021)

12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network. - Zhixuan Wang; Le Ye; Ying Liu 069; Peng Zhou; Zhichao Tan; Haitao Fan; Yihan Zhang 002; Jiayoon Ru; Yangyuan Wang; Ru Huang 001 (ISSCC, 2021)

Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. - Heyi Li; Zhichao Tan; Yuanxin Bao; Han Xiao 006; Hao Zhang 119; Kaixuan Du; Linxiao Shen; Jiayoon Ru; Yihan Zhang 002; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network. - Zhixuan Wang; Ying Liu 069; Peng Zhou; Zhichao Tan; Haitao Fan; Yihan Zhang 002; Linxiao Shen; Jiayoon Ru; Yangyuan Wang; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. - Zhixuan Wang; Hao Zhang 119; Yihan Zhang 002; Linxiao Shen; Jiayoon Ru; Haitao Fan; Zhichao Tan; Yangyuan Wang; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process. - Zhixuan Wang; Le Ye; Qianqian Huang; Kaixuan Du; Zhichao Tan; Yangyuan Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method. - Zhixuan Wang; Le Ye; Qianqian Huang; Yangyuan Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems. - Le Ye; Zhixuan Wang; Ying Liu 069; Peiyu Chen; Heyi Li; Hao Zhang 119; Meng Wu 005; Wei He; Linxiao Shen; Yihan Zhang 002; Zhichao Tan; Yangyuan Wang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme. - Hao Zhang 119; Linxiao Shen; Shichuang Zhang; Heyi Li; Yihan Zhang 002; Zhichao Tan; Ru Huang 001; Le Ye (CICC, 2022)

DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. - Yikan Qiu; Yufei Ma 002; Wentao Zhao; Meng Wu 005; Le Ye; Ru Huang 001 (ICCAD, 2022)

A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique. - Xinhang Xu; Siyuan Ye; Jihang Gao; Yihan Zhang 002; Linxiao Shen; Le Ye (ISCAS, 2022)

Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET. - Chang Xue; Yihan Zhang 002; Peiyu Chen; Mingwei Zhu; Tianqiao Wu; Meng Wu 005; Yandong He; Le Ye (ISCAS, 2022)

A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique. - Yaopeng Hu; Yibo Zhao 003; Wanyuan Qu; Le Ye; Menglian Zhao; Zhichao Tan (ISSCC, 2022)

An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Zhixuan Wang; Wei He; Linxiao Shen; Yihan Zhang 002; Peiyu Chen; Meng Wu 005; Hao Zhang 119; Peng Zhou; Jinguang Liu; Guangyu Sun 003; Jiayoon Ru; et al. (ISSCC, 2022)

A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC. - Yu-Yan Liu; Menglian Zhao; Yibo Zhao 003; Xiaopeng Yu 002; Nianxiong Nick Tan; Le Ye; Zhichao Tan (ISSCC, 2022)

Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. - Yihan Zhang 002; Chang Xue; Xiao Wang; Tianyi Liu; Jihang Gao; Peiyu Chen; Jinguang Liu; Linan Sun; Linxiao Shen; Jiayoon Ru; Le Ye; Ru Huang 001 (ISSCC, 2022)

A 4-μW Bandwidth/Power Scalable Delta-Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers. - Menglian Zhao; Yibo Zhao 003; Huajun Zhang 001; Yaopeng Hu; Yuanxin Bao; Le Ye; Wanyuan Qu; Zhichao Tan (IEEE J. Solid State Circuits, 2022)

A 16-bit 300-kS/s foreground calibration SAR ADC with single-ended/differential configurable input modes. - Yuanxin Bao; Le Ye (Microelectron. J., 2022)

A power-efficient acquisition front end for the Li-ion battery management systems. - Yuanxin Bao; Le Ye (Microelectron. J., 2022)

A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications. - Renjie Wei; Kaifeng Wang; Zhixuan Wang; Libo Yang; Fangxing Zhang; Yongqin Wu; Ye Ren; Le Ye; Lining Zhang; Weihai Bu; Ru Huang 001; Qianqian Huang (ASICON, 2023)

RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. - Peiyu Chen; Meng Wu 005; Yufei Ma 002; Le Ye; Ru Huang 001 (ASP-DAC, 2023)

A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. - Ying Liu 069; Zhiyuan Chen 009; Zhixuan Wang; Wentao Zhao; Wei He; Jianfeng Zhu; Oijun Wang; Ning Zhang; Tianyu Jia; Yufei Ma 002; Le Ye; Ru Huang 001 (CICC, 2023)

A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. - Yanchi Dong; Tianyu Jia; Kaixuan Du; Yiqi Jing; Qijun Wang; Pixian Zhan; Yadong Zhang; Fengyun Yan; Yufei Ma 002; Yun Liang 001; Le Ye; Ru Huang 001 (DAC, 2023)

A 1.2V 62.2dB SNDR SAR-Assisted Event-Driven Clockless Level-Crossing ADC for Time-Sparse Signal Acquisition. - Mengyu Li; Shuang Song 003; Wanyuan Qu; Le Ye; Menglian Zhao; Zhichao Tan (ESSCIRC, 2023)

A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. - Xinhang Xu; Linxiao Shen; Siyuan Ye; Jiayi Wu; Zhuoyi Chen; Jihang Gao; Jiajia Cui; Yihan Zhang 002; Ru Huang 001; Le Ye (ESSCIRC, 2023)

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology. - Kaifeng Wang; Yongqin Wu; Ye Ren; Renjie Wei; Zerui Chen; Jianfeng Hang; Zhixuan Wang; Fangxing Zhang; Lining Zhang; Chunyu Peng; Xiulong Wu; Le Ye; et al. (ESSDERC, 2023)

ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions. - Xiuping Cui; Size Zheng 001; Tianyu Jia; Le Ye; Yun Liang 001 (ICCAD, 2023)

An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications. - Yiqi Jing; Zhixuan Wang; Linxiao Shen; Yihan Zhang 002; Peiyu Chen; Jiayoon Ru; Le Ye (ISCAS, 2023)

DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. - Yiqi Jing; Yiyang Sun; Xiao Wang; Wentao Zhao; Meng Wu 005; Fengyun Yan; Yufei Ma 002; Le Ye; Tianyu Jia (ISLPED, 2023)

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. - Peiyu Chen; Meng Wu 005; Wentao Zhao; Jiajia Cui; Zhixuan Wang; Yadong Zhang; Qijun Wang; Jiayoon Ru; Linxiao Shen; Tianyu Jia; Yufei Ma 002; Le Ye; et al. (ISSCC, 2023)

A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. - Jihang Gao; Linxiao Shen; Heyi Li; Siyuan Ye; Jie Li; Xinhang Xu; Jiajia Cui; Yunhung Gao; Ru Huang 001; Le Ye (ISSCC, 2023)

A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control. - Yihan Zhang 002; You You; Wenjie Ren; Xinhang Xu; Linxiao Shen; Jiayoon Ru; Ru Huang 001; Le Ye (ISSCC, 2023)

A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC. - Yuyan Liu; Menglian Zhao; Yibo Zhao 003; Xiaopeng Yu 002; Nianxiong Nick Tan; Le Ye; Zhichao Tan (IEEE J. Solid State Circuits, 2023)

A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC. - Lingxin Meng; Yaopeng Hu; Yibo Zhao 003; Wanyuan Qu; Le Ye; Menglian Zhao; Zhichao Tan (IEEE J. Solid State Circuits, 2023)

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Yufei Ma 002; Wei He; Zhixuan Wang; Linxiao Shen; Jiayoon Ru; Ru Huang 001; Le Ye (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 1 V 1.07 μW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC. - Zhaonan Lu; Huaikun Ji; Wanyuan Qu; Le Ye; Menglian Zhao; Zhichao Tan (IEEE J. Solid State Circuits, 2023)

Research progress on low-power artificial intelligence of things (AIoT) chip design. - Le Ye; Zhixuan Wang; Tianyu Jia; Yufei Ma 002; Linxiao Shen; Yihan Zhang 002; Heyi Li; Peiyu Chen; Meng Wu 005; Ying Liu 069; Yiqi Jing; Hao Zhang 119; et al. (Sci. China Inf. Sci., 2023)

An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. - Jie Li; Linxiao Shen; Siyuan Ye; Jihang Gao; Jiajia Cui; Xinhang Xu; Zhuoyi Chen; Yaohui Luan; Yuanxin Bao; Ru Huang 001; Le Ye (CICC, 2024)

Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. - Yikan Qiu; Yufei Ma 002; Meng Wu 005; Yifan Jia 009; Xinyu Qu; Zecheng Zhou; Jincheng Lou; Tianyu Jia; Le Ye; Ru Huang 001 (CICC, 2024)

S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. - Meng Wu 005; Wenjie Ren; Peiyu Chen; Wentao Zhao; Yiqi Jing; Jiayoon Ru; Zhixuan Wang; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (CICC, 2024)

An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. - Zhiyuan Chen 009; Yufei Ma 002; Keyi Li; Yifan Jia 009; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (DAC, 2024)

AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. - Yiqi Jing; Meng Wu 005; Jiaqi Zhou; Yiyang Sun; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (DAC, 2024)

SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning. - Mingxuan Li; Qinzhe Zhi; Yanchi Dong; Le Ye; Tianyu Jia (DAC, 2024)

Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs. - Yanchi Dong; Xueping Liu; Xiaochen Hao; Yun Liang 001; Ru Huang 001; Le Ye; Tianyu Jia (ICCAD, 2024)

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. - Zhuoyi Chen; Linxiao Shen; Siyuan Ye; Jihang Gao; Jie Li; Jiajia Cui; Xinhang Xu; Yaohui Luan; Hao Zhang 119; Le Ye; Ru Huang 001 (ISSCC, 2024)

30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. - Ying Liu 069; Yufei Ma 002; Ninghui Shang; Tianhao Zhao; Peiyu Chen; Meng Wu 005; Jiayoon Ru; Tianyu Jia; Le Ye; Zhixuan Wang; Ru Huang 001 (ISSCC, 2024)

3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. - Xinhang Xu; Siyuan Ye; Yaohui Luan; Jihang Gao; Jie Li; Jiajia Cui; Hao Zhang 119; Ru Huang 001; Linxiao Shen; Le Ye (ISSCC, 2024)

9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. - Siyuan Ye; Linxiao Shen; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Hao Zhang 119; Xing Zhang 002; Le Ye; Ru Huang 001 (ISSCC, 2024)

A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. - Yanchi Dong; Xueping Liu; Kangbo Bai; Guoxiang Li; Meng Wu 005; Yiqi Jing; Yihan Zhang 002; Pixian Zhan; Yadong Zhang; Yufei Ma 002; Ru Huang 001; Le Ye; et al. (VLSI Technology and Circuits, 2024)

A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC. - Heyi Li; Kaixuan Du; Yuanxin Bao; Yanchi Dong; Jiayoon Ru; Han Xiao 006; Hao Zhang 119; Zhixuan Wang; Yi Zhong; Linxiao Shen; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network. - Ying Liu 069; Zhiyuan Chen 009; Wentao Zhao; Tianhao Zhao; Tianyu Jia; Zhixuan Wang; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. - Yufei Ma 002; Yikan Qiu; Wentao Zhao; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Single-Ended SAR ADC With Fully Differential DAC Switching Scheme for IoT Applications. - Kaixuan Du; Maoqiang Liu; Zhixuan Wang; Heyi Li; Yuanxin Bao; Linxiao Shen; Le Ye (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization. - Yiyang Sun; Peiran Yan; Yiqi Jing; Le Ye; Tianyu Jia (ASP-DAC, 2025)

Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition. - Zhiyuan Chen 009; Keyi Li; Yifan Jia 009; Le Ye; Yufei Ma 002 (CVPR, 2025)

Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs. - Zhantong Zhu; Hongou Li; Wenjie Ren; Meng Wu 005; Le Ye; Ru Huang 001; Tianyu Jia (DATE, 2025)

A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor. - Xueping Liu; Le Ye; Tianyu Jia (ISCAS, 2025)

37.6 A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation. - Yiqi Jing; Jiaqi Zhou; Yiyang Sun; Siyuan He; Peiyu Chen; Ru Huang 001; Le Ye; Tianyu Jia (ISSCC, 2025)

13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction. - Ying Liu 069; Jie Li; Qining Zhang; Tianhao Zhao; Chenhao Shi; Ninghui Shang; Peiyu Chen; Xiaohuan Ge; Yufei Ma 002; Linxiao Shen; Zhixuan Wang; Ru Huang 001; et al. (ISSCC, 2025)

An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS. - Jihang Gao; Siyuan Ye; Jie Li; Xinhang Xu; Zhuoyi Chen; Jiajia Cui; Yaohui Luan; Ru Huang 001; Le Ye; Linxiao Shen (IEEE J. Solid State Circuits, 2025)

A 62.2dB SNDR Event-Driven Level-Crossing ADC With SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical Signal Acquisition. - Mengyu Li; Yi Huo; Shuang Song 003; Wanyuan Qu; Le Ye; Menglian Zhao; Zhichao Tan (IEEE Trans. Biomed. Circuits Syst., 2025)

EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge. - Kangbo Bai; Le Ye; Ru Huang 001; Tianyu Jia (CoRR, 2025)

A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting. - Siyuan Ye; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Yaohui Luan; Le Ye; Xing Zhang 002; Ru Huang 001; Linxiao Shen (IEEE J. Solid State Circuits, 2025)

A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. - Peiyu Chen; Wentao Zhao; Meng Wu 005; Linxiao Shen; Tianyu Jia; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE J. Solid State Circuits, 2025)