Development of Fertile Egg Detection and Incubation System Using Image Processing and Automatic Candling. - Lean Karlo S. Tolentino; Emmanuel Justine G. Enrico; Ralph Lawrence M. Listanco; Mark Anthony M. Ramirez; Ted Lorenz U. Renon; Mark Rikko B. Samson (TENCON, 2018)

Development of an IoT-based Aquaponics Monitoring and Correction System with Temperature-Controlled Greenhouse. - Lean Karlo S. Tolentino; Edmon O. Fernandez; Romeo L. Jorda; Shayne Nathalie D. Amora; Daniel Kristopher T. Bartolata; Joshua Ricart V. Sarucam; June Carlo L. Sobrepeña; Kristine Yvonne P. Sombol (ISOCC, 2019)

Automated Smart Wick System-Based Microfarm Using Internet of Things. - Romeo Jorda Jr.; C. Alcabasa; A. Buhay; E. C. Dela Cruz; J. P. Mendoza; A. Tolentino; Lean Karlo S. Tolentino; E. Fernandez; August Thio-ac; Jessica Velasco; Nilo Arago (CoRR, 2019)

Efficiency Improvement of Commercially Available MPPT Controllers Using Boost Converter. - Lean Karlo S. Tolentino; Dan Frederico P. Abacco; Mar Jun M. Siquihod (CoRR, 2019)

Utilization of e-Nose Sensory Modality as Add-On Feature for Advanced Driver Assistance System. - Ira C. Valenzuela; Lean Karlo S. Tolentino; Ronnie O. Serfa Juan (CoRR, 2019)

A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. - Tzung-Je Lee; Wen-Jian Su; Lean Karlo S. Tolentino; Chua-Chin Wang (APCCAS, 2021)

An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. - Chua-Chin Wang; Oliver Lexter July A. Jose; Po-Kai Su; Lean Karlo S. Tolentino; Ralph Gerard B. Sangalang; Jessica Velasco; Tzung-Je Lee (Microelectron. J., 2021)

A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM. - Chua-Chin Wang; Lean Karlo S. Tolentino; Chia-Yi Huang; Chia-Hung Yeh (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. - Jyoshnavi Akiri; Lean Karlo S. Tolentino; Lung-Jieh Yang; Balasubramanian Esakki; Sivaperumal Sampath; Chua-Chin Wang (APCCAS, 2022)

A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture. - Li Lin; Lean Karlo S. Tolentino; Chua-Chin Wang (ISCAS, 2022)

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. - Jhih-Ying Ke; Lean Karlo S. Tolentino; Cheng-Yao Lo; Tzung-Je Lee; Chua-Chin Wang (APCCAS, 2023)

Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. - Ralph Gerard B. Sangalang; You-Wei Shen; Shiva Reddy; Lean Karlo S. Tolentino; Chua-Chin Wang (ASICON, 2023)

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. - Chua-Chin Wang; Oliver Lexter July A. Jose; Wen-Shou Yang; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Tzung-Je Lee (Circuits Syst. Signal Process., 2023)

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. - Chua-Chin Wang; Lean Karlo S. Tolentino; Shao-Wei Lu; Oliver Lexter July A. Jose; Ralph Gerard B. Sangalang; Tzung-Je Lee; Pang-Yen Lou; Wei-Chih Chang (Integr., 2023)

A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. - Ralph Gerard B. Sangalang; Shiva Reddy; Lean Karlo S. Tolentino; You-Wei Shen; Oliver Lexter July A. Jose; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. - Jhih-Ying Ke; Lean Karlo Santos Tolentino; Cheng-Yao Lo; Tzung-Je Lee; Chua-Chin Wang (AICAS, 2024)

A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process. - Cheng-Yao Lo; Lean Karlo Santos Tolentino; Jhih-Ying Ke; Jeffrey S. Walling; Yang Yi 002; Chua-Chin Wang (AICAS, 2024)

A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. - Soumika Majumder; Lean Karlo Santos Tolentino; Oliver Lexter July Alvarez Jose; Venkata Naveen Kolakaluri; Mitch Ming-Chi Chou; Chua-Chin Wang (ISOCC, 2024)

A single-chip PFM-controlled LED driver with 0.5% illuminance variation. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Pang-Yen Lou; Chen-Cheng-Hung Hung; Pradyumna Vellanki; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Tirso A. Ronquillo (Microelectron. J., 2024)

A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. - Oliver Lexter July A. Jose; Venkata Naveen Kolakaluri; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Chua-Chin Wang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. - Chua-Chin Wang; Oliver Lexter July A. Jose; Li Lin; Lean Karlo S. Tolentino; Ralph Gerard B. Sangalang; Anela L. Salvador (Circuits Syst. Signal Process., 2024)

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Jhih-Ying Ke; Cheng-Yao Lo; Tzung-Je Lee; Lean Karlo Santos Tolentino (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)