An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing. - Benjamín T. Reyes; Laura Biolato; Agustin C. Galetto; Leandro Passetti; Fredy Solis; Mario R. Hueda (LASCAS, 2018)

An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC. - Benjamín T. Reyes; Laura Biolato; Agustin C. Galetto; Leandro Passetti; Fredy Solis; Mario R. Hueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Backpropagation-Based Background Compensation of Frequency Interleaved ADC for Coherent Optical Receivers. - Leandro Passetti; Agustin C. Galetto; Diego J. Hernando; Damián A. Morero; Benjamín T. Reyes; Mario R. Hueda (ISCAS, 2020)

Reduced Complexity Backpropagation-Based Adaptive Compensation of Frequency Interleaved ADC for Digital Communication Receivers. - Leandro Passetti; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (ISCAS, 2021)

A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS. - Fredy Solis; Álvaro Fernandez Bocco; Agustin C. Galetto; Leandro Passetti; Mario R. Hueda; Benjamín T. Reyes (Int. J. Circuit Theory Appl., 2021)

Evaluation of the Performance Impact of Clock Jitter and Phase Noise in a Two-Band Frequency-Interleaved ADC. - Leandro Passetti; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (ICECS, 2023)

Adaptive Digital Compensation of Analog Impairments in Frequency Interleaved ADC for Next-Generation High-Speed Communication Receivers. - Leandro Passetti; Damián A. Morero; Benjamín T. Reyes; Mario R. Hueda (IEEE Access, 2023)