Efficent suboptimal state assignment for large sequential machines. - Lech Józwiak (EURO-DAC, 1990)

Simultaneous decompositions of sequential machines. - Lech Józwiak (Microprocessing and Microprogramming, 1990)

An efficient for the sequential general decomposition of sequential machines. - Lech Józwiak; J. C. Kolsteren (Microprocessing and Microprogramming, 1991)

An Efficient Heuristic Method for State Assignment of Large Sequential Machines. - Lech Józwiak (J. Circuits Syst. Comput., 1992)

On the use of OR-BDDs for test generation. - Lech Józwiak; Hein Mijland (Microprocess. Microprogramming, 1992)

Algorithms and tools for VLSI design. - Lech Józwiak (Microprocess. Microprogramming, 1993)

Efficient decomposition of assigned sequential machines and Boolean functions for PLD implementations. - Lech Józwiak; Frank Wolf (Electronic Technology Directions, 1995)

Guest Editor's Introduction. - Lech Józwiak (VLSI Design, 1995)

General Decomposition and Its Use in Digital Circuit Synthesis. - Lech Józwiak (VLSI Design, 1995)

Division-Based Versus General Decomposition- Based Multiple-Level Logic Synthesis. - Frank Volf; Lech Józwiak; Mario Stevens (VLSI Design, 1995)

Quality-Driven Decision Making Methodology for System-Level Design. - Lech Józwiak; Sien-An Ong (EUROMICRO, 1996)

Information Relationships and Measures An Analysis Apparatus for Efficient Information System Synthesis. - Lech Józwiak (EUROMICRO, 1997)

On the use of term trees for effective and efficient test pattern generation. - Lech Józwiak (EUROMICRO, 1997)

Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures. - Sanof Mohamed; Marek A. Perkowski; Lech Józwiak (EUROMICRO, 1997)

Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models. - Sien-An Ong; Kari Tiensyrjä; Lech Józwiak (EUROMICRO, 1997)

Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. - Stan Grygiel; Marek A. Perkowski; Malgorzata Marek-Sadowska; Tadeusz Luba; Lech Józwiak (ISMVL, 1997)

Decomposition of Multiple-Valued Relations . - Marek A. Perkowski; Malgorzata Marek-Sadowska; Lech Józwiak; Tadeusz Luba; Stan Grygiel; Miroslawa Nowicka; Rahul Malvi; Zhi Wang; Jin S. Zhang (ISMVL, 1997)

An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables. - Michael Burns; Marek A. Perkowski; Lech Józwiak (EUROMICRO, 1998)

Solving Synthesis Problems with Genetic Algorithms. - Lech Józwiak; Niek Ederveen; Adam Postula (EUROMICRO, 1998)

Design of Self-Synchronized Component FSMs for Self-Timed Systems. - Loc Bao Nguen; Marek A. Perkowski; Lech Józwiak (EUROMICRO, 1998)

Automated Synthesis of Interleaved Memory Systems for Custom Computing Machine. - Adam Postula; Song Chen; Lech Józwiak; David Abramson 001 (EUROMICRO, 1998)

Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. - Mariusz Rawski; Tadeusz Luba; Lech Józwiak; Artur Chojnacki (EUROMICRO, 1998)

Analysis and Synthesis of Information Systems with Information Relationships and Measures. - Lech Józwiak (Rough Sets and Current Trends in Computing, 1998)

Application of the Information Measures to Input Support Selection in Functional Decomposition. - Mariusz Rawski; Lech Józwiak; Artur Chojnacki (Rough Sets and Current Trends in Computing, 1998)

Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention. - Song Chen; Adam Postula; Lech Józwiak (EUROMICRO, 1999)

Digital System Design: Architectures, Methods and Tools. - Lech Józwiak (EUROMICRO, 1999)

Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric Functions. - Lech Józwiak; Artur Chojnacki (EUROMICRO, 1999)

Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine. - Torrey Lewis; Marek A. Perkowski; Lech Józwiak (EUROMICRO, 1999)

The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. - Mariusz Rawski; Lech Józwiak; Tadeusz Luba (EUROMICRO, 1999)

Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. - Mariusz Rawski; Lech Józwiak; Tadeusz Luba (EUROMICRO, 1999)

Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. - Rafal Rzechowski; Tadeusz Luba; Lech Józwiak (EUROMICRO, 1999)

Information Relationships and Measures in Application to Logic Design. - Lech Józwiak (ISMVL, 1999)

A New State Assignment Method Targeting FPGA Implementations. - Lech Józwiak; Aleksander Slusarczyk (EUROMICRO, 2000)

Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. - Artur Chojnacki; Lech Józwiak (ISMVL, 2000)

Quality-Driven System-on-a-Chip Design. - Lech Józwiak (ISQED, 2000)

High-quality sub-function construction in functional decomposition based on information relationship measures. - Lech Józwiak; Artur Chojnacki (DATE, 2001)

Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. - Lech Józwiak; Artur Chojnacki (DSD, 2001)

Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. - Lech Józwiak; Artur Chojnacki; Aleksander Slusarczyk (DSD, 2001)

Regular Realization of Symmetric Functions Using Reversible Logic. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Xiaoyu Song; Anas Al-Rabadi; Bart Massey; Pawel Kerntopf; Andrzej Buller; Lech Józwiak; Alan J. Coppola (DSD, 2001)

High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. - Artur Chojnacki; Lech Józwiak (ISQED, 2001)

Modern methods and tools in digital system design. - Lech Józwiak (J. Syst. Archit., 2001)

Quality-driven design in the system-on-a-chip era: Why and how? - Lech Józwiak (J. Syst. Archit., 2001)

Symbolic two-dimensional minimization of strongly unspecified finite state machines. - Marek A. Perkowski; Lech Józwiak; William Zhao (J. Syst. Archit., 2001)

Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures. - Mariusz Rawski; Lech Józwiak; Tadeusz Luba (J. Syst. Archit., 2001)

Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. - Aleksander Slusarczyk; Lech Józwiak (ISQED, 2002)

Genetic engineering versus natural evolution: Genetic algorithms with deterministic operators. - Lech Józwiak; Adam Postula (J. Syst. Archit., 2002)

Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach. - Marek A. Perkowski; David Foote; Qihong Chen; Anas Al-Rabadi; Lech Józwiak (IEEE Micro, 2002)

Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture. - Marek A. Perkowski; David Foote; Qihong Chen; Anas Al-Rabadi; Lech Józwiak (IEEE Micro, 2002)

Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits. - Lech Józwiak; Aleksander Slusarczyk; Marek A. Perkowski (VLSI Design, 2002)

Information-driven Library-based Circuit Synthesis. - Lech Józwiak; Szymon Bieganski; Artur Chojnacki (DSD, 2003)

Advanced AI Search Techniques in Modern Digital Circuit Synthesis. - Lech Józwiak (Artif. Intell. Rev., 2003)

Special-issue on reconfigurable systems. - Martyn Edwards; Lech Józwiak (J. Syst. Archit., 2003)

Preface. - Martyn Edwards; Lech Józwiak (J. Syst. Archit., 2003)

Effective and efficient FPGA synthesis through general functional decomposition. - Lech Józwiak; Artur Chojnacki (J. Syst. Archit., 2003)

Fast and compact sequential circuits for the FPGA-based reconfigurable systems. - Lech Józwiak; Aleksander Slusarczyk; Artur Chojnacki (J. Syst. Archit., 2003)

Life-Inspired Systems. - Lech Józwiak (DSD, 2004)

Information Trans-Coders in Information-Driven Circuit Synthesis. - Lech Józwiak; Szymon Bieganski (DSD, 2004)

An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. - Lech Józwiak; Dominik Gawlowski; Aleksander Slusarczyk (DSD, 2004)

General decomposition of incompletely specified sequential machines with multi-state behavior realization. - Lech Józwiak; Aleksander Slusarczyk (J. Syst. Archit., 2004)

High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. - Lech Józwiak; Szymon Bieganski (DSD, 2005)

Plenary Session 2P. - Lech Józwiak; Kaustav Banerjee (ISQED, 2005)

Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. - Lech Józwiak (IWSOC, 2005)

Information-driven circuit synthesis with the pre-characterized gate libraries. - Lech Józwiak; Szymon Bieganski; Artur Chojnacki (J. Syst. Archit., 2005)

Reconfigurable embedded systems: Synthesis, design and application. - Henry Selvaraj; Lech Józwiak (J. Syst. Archit., 2005)

Life-Inspired Systems and Their Quality-Driven Design. - Lech Józwiak (ARCS, 2006)

Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. - Lech Józwiak; Sien-An Ong (DSD, 2006)

Multi-objective Optimal FSM State Assignment. - Lech Józwiak; Aleksander Slusarczyk; Dominik Gawlowski (DSD, 2006)

Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. - Lech Józwiak; Dominik Gawlowski; Aleksander Slusarczyk (ICSAMOS, 2006)

Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. - Lech Józwiak (ISQED, 2007)

Quality Driven Manufacturing and SOC Designs. - Srikanth Venkataraman; Nagesh Nagapalli; Lech Józwiak (ISQED, 2007)

Technology Library Modelling for Information-driven Circuit Synthesis. - Lech Józwiak; Szymon Bieganski (DSD, 2008)

High-Quality Circuit Synthesis for Modern Technologies. - Lech Józwiak; Artur Chojnacki; Aleksander Slusarczyk (ISQED, 2008)

Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. - Lech Józwiak; Alexander Douglas (ITNG, 2008)

Quality-driven model-based architecture synthesis for real-time embedded SoCs. - Lech Józwiak; Sien-An Ong (J. Syst. Archit., 2008)

Editorial. - Venkatesan Muthukumar; Lech Józwiak (J. Syst. Archit., 2008)

Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. - Yahya Jan; Lech Józwiak (ARC, 2009)

CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. - Yahya Jan; Lech Józwiak (SAMOS, 2009)

Modern Architectures for Embedded Reconfigurable Systems - a Survey. - Lech Józwiak; Nadia Nedjah (J. Circuits Syst. Comput., 2009)

Quality-driven methodology for demanding accelerator design. - Lech Józwiak; Yahya Jan (ISQED, 2010)

Architecture Design of Reconfigurable Accelerators for Demanding Applications. - Lech Józwiak; Yahya Jan (ITNG, 2010)

Quality-driven SoC architecture synthesis for embedded applications. - Lech Józwiak (SoCC, 2010)

Modern development methods and tools for embedded reconfigurable systems: A survey. - Lech Józwiak; Nadia Nedjah; Miguel E. Figueroa (Integr., 2010)

Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits. - Michal Bryk; Lech Józwiak; Wieslaw Kuzmicz (DSD, 2011)

A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (DSD, 2011)

Massively Parallel Identification of Intersection Points for GPGPU Ray Tracing. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (ICA3PP (2), 2011)

A parallel architecture for ray-tracing with an embedded intersection algorithm. - Alexandre Solon Nery; Nadia Nedjah; Felipe Maia Galvão França; Lech Józwiak (ISCAS, 2011)

Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs. - Lech Józwiak; Menno Lindwer (PDP, 2011)

Advanced Architectures for Highly-demanding Embedded and Pervasive Applications. - Lech Józwiak (PECCS, 2011)

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study. - Rosilde Corvino; Erkan Diken; Abdoulaye Gamatié; Lech Józwiak (DSD, 2012)

Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. - Roel Jordans; Rosilde Corvino; Lech Józwiak (DSD, 2012)

ASAM: Automatic Architecture Synthesis and Application Mapping. - Lech Józwiak; Menno Lindwer; Rosilde Corvino; Paolo Meloni; Laura Micconi; Jan Madsen; Erkan Diken; Deepak Gangadharan; Roel Jordans; Sebastiano Pomata; Paul Pop; Giuseppe Tuveri; et al. (DSD, 2012)

Design space exploration in application-specific hardware synthesis for multiple communicating nested loops. - Rosilde Corvino; Abdoulaye Gamatié; Marc Geilen; Lech Józwiak (ICSAMOS, 2012)

Interactive Volume Rendering Based on Ray-Casting for Multi-core Architectures. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (VECPAR, 2012)

Scalable communication architectures for massively parallel hardware multi-processors. - Yahya Jan; Lech Józwiak (J. Parallel Distributed Comput., 2012)

Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors. - Yahya Jan; Lech Józwiak (VLSI Design, 2012)

Exploring processor parallelism: Estimation methods and optimization strategies. - Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal (DDECS, 2013)

An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors. - Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal (DSD, 2013)

A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak; Henk Corporaal (ICA3PP (1), 2013)

HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications. - Lech Józwiak (ISVLSI, 2013)

Hardware Multi-processor Design for Highly-Demanding Applications. - Lech Józwiak; Yahya Jan (ITNG, 2013)

Rapid and accurate energy estimation of vector processing in VLIW ASIPs. - Erkan Diken; Rosilde Corvino; Lech Józwiak (MECO, 2013)

Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. - Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal (MECO, 2013)

Quality-driven model-based design of multi-processor embedded systems for highlydemanding applications. - Lech Józwiak; Jan Madsen (MECO, 2013)

Hierarchical DSE for multi-ASIP platforms. - Laura Micconi; Rosilde Corvino; Deepak Gangadharan; Jan Madsen; Paul Pop; Lech Józwiak (MECO, 2013)

Design of massively parallel hardware multi-processors for highly-demanding embedded applications. - Lech Józwiak; Yahya Jan (Microprocess. Microsystems, 2013)

ASAM: Automatic architecture synthesis and application mapping. - Lech Józwiak; Menno Lindwer; Rosilde Corvino; Paolo Meloni; Laura Micconi; Jan Madsen; Erkan Diken; Deepak Gangadharan; Roel Jordans; Sebastiano Pomata; Paul Pop; Giuseppe Tuveri; et al. (Microprocess. Microsystems, 2013)

Preface. - Francesco Leporati; Lech Józwiak (Microprocess. Microsystems, 2013)

Application-specific processors and system-on-chips for embedded and pervasive applications. - Nadia Nedjah; Lech Józwiak; Luiza de Macedo Mourelle (Microprocess. Microsystems, 2013)

Hardware reuse in modern application-specific processors and accelerators. - Alexandre Solon Nery; Lech Józwiak; Menno Lindwer; Mauro Cocco; Nadia Nedjah; Felipe M. G. França (Microprocess. Microsystems, 2013)

Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (Microprocess. Microsystems, 2013)

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching. - Roel Jordans; Erkan Diken; Lech Józwiak; Henk Corporaal (DDECS, 2014)

A framework for automatic custom instruction identification on multi-issue ASIPs. - Alexandre Solon Nery; Nadia Nedjah; Felipe Maia Galvão França; Lech Józwiak; Henk Corporaal (INDIN, 2014)

Automatic complex instruction identification for efficient application mapping onto ASIPs. - Alexandre Solon Nery; Nadia Nedjah; Felipe Maia Galvão França; Lech Józwiak; Henk Corporaal (LASCAS, 2014)

Construction and exploitation of VLIW asips with multiple vector-widths. - Erkan Diken; Roel Jordans; Lech Józwiak; Henk Corporaal (MECO, 2014)

Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. - Roel Jordans; Lech Józwiak; Henk Corporaal (MECO, 2014)

Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. - Erkan Diken; Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal; Felipe Augusto Chies (Microprocess. Microsystems, 2014)

Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding. - Yahya Jan; Lech Józwiak (Microprocess. Microsystems, 2014)

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths. - Erkan Diken; Martin J. O'Riordan; Roel Jordans; Lech Józwiak; Henk Corporaal; David Moloney (ASAP, 2015)

FPGA-accelerated simulation engine for non-viral gene delivery. - David Perlaza; Adam Postula; Lech Józwiak; Tadeusz A. Wysocki (ICSPCS, 2015)

A compilation technique and performance profits for VLIW with heterogeneous vectors. - Erkan Diken; Lech Józwiak (MECO, 2015)

MICPRO special issue on European projects in embedded system design 2014. - Francesco Leporati; Lech Józwiak (Microprocess. Microsystems, 2015)

Wearable and mobile systems. - Lech Józwiak (MECO, 2016)

Message from the chairs. - Lech Józwiak; Radovan Stojanovic; Budimir Lutovac (MECO, 2016)

Special Section on European Projects in Embedded System Design 2015. - Francesco Leporati; Lech Józwiak (Microprocess. Microsystems, 2016)

Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. - Roel Jordans; Lech Józwiak; Henk Corporaal; Rosilde Corvino (Microprocess. Microsystems, 2017)

Advanced mobile and wearable systems. - Lech Józwiak (Microprocess. Microsystems, 2017)

Special issue on cyber-physical systems. - Radovan Stojanovic; Lech Józwiak (Microprocess. Microsystems, 2017)

An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures. - Tong Geng; Erkan Diken; Tianqi Wang; Lech Józwiak; Martin C. Herbordt (HPEC, 2018)

Quality-driven Design of Deep Neural Network Accelerators for CPS and IoT Applications. - Yahya Jan; Lech Józwiak (MECO, 2021)

Editorial: Recent developments and the future of MICPRO. - Lech Józwiak; Francesco Leporati (Microprocess. Microsystems, 2023)

Quality-driven design of deep neural network hardware accelerators for low power CPS and IoT applications. - Yahya Jan; Lech Józwiak (Microprocess. Microsystems, 2024)