Statistical time borrowing for pulsed-latch circuit designs. - Seungwhun Paik; Lee-eun Yu; Youngsoo Shin (ASP-DAC, 2010)

Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. - Lee-eun Yu; Changsik Shin; Seungwhun Paik; Jing-Jia Liou; Youngsoo Shin (J. Circuits Syst. Comput., 2011)