Modeling of the distributed gate RC effect in MOSFET's. - Lee-Sup Kim; Robert W. Dutton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Metastability of CMOS latch/flip-flop. - Lee-Sup Kim; Robert W. Dutton (IEEE J. Solid State Circuits, 1990)

A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. - Masataka Matsui; Hiroyuki Hara; Yoshiharu Uetani; Lee-Sup Kim; Tetsu Nagamatsu; Yoshinori Watanabe; Akihiko Chiba; Kouji Matsuda; Takayasu Sakurai (IEEE J. Solid State Circuits, 1994)

A new 4-2 adder and booth selector for low power MAC unit. - Bum-Sik Kim; Dae-Hyum Chung; Lee-Sup Kim (ISLPED, 1997)

A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics. - Hyunchul Shin; Jin-Aeon Lee; Lee-Sup Kim (ICCD, 1998)

A Memory Architecture with 4-Address Configurations for Video Signal Processing. - Sunho Chang; Jong-Sun Kim; Lee-Sup Kim (DATE, 2000)

Single-Pass Full-Screen Hardware Accelerated Antialiasing. - Jin-Aeon Lee; Lee-Sup Kim (Workshop on Graphics Hardware, 2000)

SPARP: a single pass antialiased rasterization processor. - Jin-Aeon Lee; Lee-Sup Kim (Comput. Graph., 2000)

Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler". - Ki-Hyuk Sung; Lee-Sup Kim (IEEE J. Solid State Circuits, 2000)

A programmable 3.2-GOPS merged DRAM logic for video signal processing. - Sunho Chang; Bum-Sik Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. Video Technol., 2000)

A real-time wavelet vector quantization algorithm and its VLSI architecture. - Seung-Kwon Paek; Lee-Sup Kim (IEEE Trans. Circuits Syst. Video Technol., 2000)

SPAF: Sub-texel Precision Anisotropic Filtering. - Hyunchul Shin; Jin-Aeon Lee; Lee-Sup Kim (Workshop on Graphics Hardware, 2001)

Design trade-off in merged DRAM logic for video signal processing. - Sunho Chang; Lee-Sup Kim (ISCAS (5), 2001)

A low power carry select adder with reduced area. - Youngjoon Kim; Lee-Sup Kim (ISCAS (4), 2001)

A high-speed pattern decoder in MPEG-4 padding block hardware accelerator. - Hyeon-Cheol Mo; Jong-Sun Kim; Lee-Sup Kim (ISCAS (2), 2001)

An advanced contrast enhancement using partially overlapped sub-block histogram equalization. - Joung-Youn Kim; Lee-Sup Kim; Seung-Ho Hwang (IEEE Trans. Circuits Syst. Video Technol., 2001)

A hardware cost minimized fast Phong shader. - Hyunchul Shin; Jin-Aeon Lee; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A ROM compression method for continuous data. - Byung-Do Yang; Lee-Sup Kim (CICC, 2002)

A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme. - Youngjoon Kim; Ki-Hyuk Sung; Lee-Sup Kim (ISCAS (1), 2002)

A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. - Byung-Do Yang; Lee-Sup Kim; Hyun-Kyu Yu (ISCAS (5), 2002)

A PN triangle generation unit for fast and simple tessellation hardware. - Kyusik Chung; Lee-Sup Kim (ISCAS (2), 2003)

A hardware-like high-level language based environment for 3D graphics architecture exploration. - Inho Lee; Joung-Youn Kim; Yeon-Ho Im; Yunseok Choi; Hyunchul Shin; Chang-Young Han; Donghyun Kim 014; Hyoungjoon Park; Young-Il Seo; Kyusik Chung; Chang-Hyo Yu; Kanghyup Chun; et al. (ISCAS (2), 2003)

A low power charge sharing ROM using dummy bit lines. - Byung-Do Yang; Lee-Sup Kim (ISCAS (5), 2003)

A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter. - Chang-Hyo Yu; Lee-Sup Kim (ISCAS (2), 2003)

A clock delayed sleep mode domino logic for wide dynamic OR gate. - Kwang-Il Oh; Lee-Sup Kim (ISLPED, 2003)

A low-power ROM using charge recycling and charge sharing techniques. - Byung-Do Yang; Lee-Sup Kim (IEEE J. Solid State Circuits, 2003)

Winscale: an image-scaling algorithm using an area pixel model. - Chun-Ho Kim; Si-Mun Seong; Jin-Aeon Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. Video Technol., 2003)

A low-power charge-recycling ROM architecture. - Byung-Do Yang; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A 250MHz-2GHz wide range delay-locked loop. - Byung-Guk Kim; Lee-Sup Kim (CICC, 2004)

Adaptive Selection of an Index in a Texture Cache. - Chun-Ho Kim; Lee-Sup Kim (ICCD, 2004)

Division-free rasterizer for perspective-correct texture filtering. - Donghyun Kim 014; Lee-Sup Kim (ISCAS (2), 2004)

A high performance low power dynamic PLA with conditional evaluation scheme. - Kwang-Il Oh; Lee-Sup Kim (ISCAS (2), 2004)

An error pattern ROM compression method for continuous data. - Byung-Do Yang; Lee-Sup Kim (ISCAS (2), 2004)

An adaptive spatial filter for early depth test. - Chang-Hyo Yu; Lee-Sup Kim (ISCAS (2), 2004)

An Efficient Fragment Processing Technique in A-Buffer Implementation. - Donghyun Kim 014; Lee-Sup Kim (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004)

A high-resolution synchronous mirror delay using successive approximation register. - Kihyuk Sung; Lee-Sup Kim (IEEE J. Solid State Circuits, 2004)

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. - Byung-Do Yang; Jang-Hong Choi; Seon-Ho Han; Lee-Sup Kim; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2004)

A 500MHz DLL with second order duty cycle corrector for low jitter. - Byung-Guk Kim; Kwang-Il Oh; Lee-Sup Kim; Dae-Woo Lee (CICC, 2005)

An 11M-triangles/sec 3D graphics clipping engine for triangle primitives. - Jaewan Bae; Donghyun Kim 014; Lee-Sup Kim (ISCAS (5), 2005)

A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware. - Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (ISCAS (5), 2005)

A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems. - Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (ISCAS (5), 2005)

Geometry engine architecture with early backface culling hardware. - Chang-Young Han; Yeon-Ho Im; Lee-Sup Kim (Comput. Graph., 2005)

An Efficient Memory Address Converter for Soc-based 3d Graphics System. - Joung-Youn Kim; Lee-Sup Kim (J. Circuits Syst. Comput., 2005)

A 250-MHz-2-GHz wide-range delay-locked loop. - Byung-Guk Kim; Lee-Sup Kim (IEEE J. Solid State Circuits, 2005)

A low-power SRAM using hierarchical bit line and local sense amplifiers. - Byung-Do Yang; Lee-Sup Kim (IEEE J. Solid State Circuits, 2005)

A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver. - Byung-Do Yang; Lee-Sup Kim (IEEE J. Solid State Circuits, 2005)

A Method to Generate Soft Shadows Using a Layered Depth Image and Warping. - Yeon-Ho Im; Chang-Young Han; Lee-Sup Kim (IEEE Trans. Vis. Comput. Graph., 2005)

An efficient texture cache for programmable vertex shaders. - Seunghyun Cho; Chang-Hyo Yu; Lee-Sup Kim (ISCAS, 2006)

Vertex cache of programmable geometry processor for mobile multimedia application. - Kyusik Chung; Chang-Hyo Yu; Lee-Sup Kim (ISCAS, 2006)

Charge-pump reducing current mismatch in DLLs and PLLs. - Kyung-Soo Ha; Lee-Sup Kim (ISCAS, 2006)

A 0.18µm CMOS 10Gb/s 1: 4 DEMUX using replica-bias circuits for optical receiver. - Ju-Pyo Hong; Kyung-Soo Ha; Lee-Sup Kim (ISCAS, 2006)

A low power SoC bus with low-leakage and low-swing technique. - Kwang-Il Oh; Seunghyun Cho; Lee-Sup Kim (ISCAS, 2006)

A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS. - Byung-Guk Kim; Lee-Sup Kim; Sangjin Byun; Hyun-Kyu Yu (ISSCC, 2006)

A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (ISSCC, 2006)

An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. - Donghyun Kim 014; Kyusik Chung; Chang-Hyo Yu; Chun-Ho Kim; Inho Lee; Jaewan Bae; Young-Jun Kim 001; Jae-Hyeon Park; Sungbeen Kim; Yong-Ha Park; Nak Hee Seong; Jin-Aeon Lee; et al. (IEEE J. Solid State Circuits, 2006)

A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth. - Hyunchul Shin; Jin-Aeon Lee; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A low-power ROM using single charge-sharing capacitor and hierarchical bit line. - Byung-Do Yang; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (CICC, 2007)

Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware. - Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (ISCAS, 2007)

A DLL with Jitter-Reduction Techniques for DRAM Interfaces. - Byung-Guk Kim; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Soo-In Cho (ISSCC, 2007)

A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine. - Seok-Hoon Kim; Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Kyusik Chung; Han Shin Lim; HyunWook Park; Lee-Sup Kim (ISSCC, 2007)

Binary Motion Estimation with Hybrid Distortion Measure. - Jong-Sun Kim; Lee-Sup Kim (IEICE Trans. Inf. Syst., 2007)

An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (IEEE J. Solid State Circuits, 2007)

Tessellation-enabled shader for a bandwidth-limited 3D graphics engine. - Kyusik Chung; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (CICC, 2008)

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme. - Kwang-Il Oh; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Kinam Kim (CICC, 2008)

A 3D graphics processor with fast 4D vector inner product units and power aware texture cache. - Jae-Sung Yoon; Donghyun Kim 014; Chang-Hyo Yu; Lee-Sup Kim (CICC, 2008)

High speed serial interface for mobile LCD driver IC. - Hyun-Kyu Jeon; Hye-Ran Kim; Jung-Min Choi; Ju-Pyo Hong; Yong-Suk Kim; Hyung-Seog Oh; Dae-Keun Han; Lee-Sup Kim (ISCAS, 2008)

Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm. - Jeong-Hyun Kim; Kyusik Chung; Young-Jun Kim 001; Seok-Hoon Kim; Lee-Sup Kim (ISCAS, 2008)

Area-efficient pixel rasterization and texture coordinate interpolation. - Donghyun Kim 014; Lee-Sup Kim (Comput. Graph., 2008)

Noise Robust Motion Refinement for Motion Compensated Noise Reduction. - Jong-Sun Kim; Lee-Sup Kim (IEICE Trans. Inf. Syst., 2008)

A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. - Byung-Guk Kim; Lee-Sup Kim; Sangjin Byun; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2008)

A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine. - Seok-Hoon Kim; Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Kyusik Chung; Han Shin Lim; Yun-Gu Lee; HyunWook Park; Jong Beom Ra; Lee-Sup Kim (IEEE J. Solid State Circuits, 2008)

An Area Efficient Early Z -Test Method for 3-D Graphics Rendering Hardware. - Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Bank-partition and Multi-fetch Scheme for Floating-point Special Function units in Multi-core Systems. - Young-Jun Kim 001; Kyusik Chung; Lee-Sup Kim; Seong Mo Park (ISCAS, 2009)

A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link. - Won-Young Lee; Lee-Sup Kim (ISCAS, 2009)

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (ISSCC, 2009)

Shader-based tessellation to save memory bandwidth in a mobile multimedia processor. - Kyusik Chung; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (Comput. Graph., 2009)

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (IEEE J. Solid State Circuits, 2009)

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces. - Byung-Guk Kim; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Soo-In Cho (IEEE J. Solid State Circuits, 2009)

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme. - Kwang-Il Oh; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Joo-Sun Choi; Kinam Kim (IEEE J. Solid State Circuits, 2009)

A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency. - Donghyun Kim 014; Lee-Sup Kim (IEEE Trans. Computers, 2009)

A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Seok-Hoon Kim; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications. - Mi-Jo Kim; Lee-Sup Kim (CICC, 2010)

Reconfigurable mobile stream processor for ray tracing. - Hong-Yun Kim; Young-Jun Kim 001; Lee-Sup Kim (CICC, 2010)

A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping. - Sang-Hye Chung; Kyu-Dong Hwang; Won-Young Lee; Lee-Sup Kim (ISCAS, 2010)

An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages. - Kyu-Dong Hwang; Lee-Sup Kim (ISCAS, 2010)

A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality. - Jae-Sung Yoon; Jeong-Hyun Kim; Hyo-Eun Kim; Won-Young Lee; Seok-Hoon Kim; Kyusik Chung; Jun-Seok Park; Lee-Sup Kim (ISSCC, 2010)

A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications. - Seok-Hoon Kim; Hong-Yun Kim; Young-Jun Kim 001; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (IEEE J. Solid State Circuits, 2010)

Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]. - Kwang-Il Oh; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Joo-Sun Choi; Kinam Kim (IEEE J. Solid State Circuits, 2010)

A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method. - Hye-Yoon Joo; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS. - Young-Ju Kim 001; Sang-Hye Chung; Lee-Sup Kim (CICC, 2011)

A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation. - Won-Young Lee; Lee-Sup Kim (ISCAS, 2011)

Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors. - Seungwook Paek; Jiehwan Oh; Sang-Hye Chung; Lee-Sup Kim (ISCAS, 2011)

A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer. - Hyo-Eun Kim; Jae-Sung Yoon; Kyu-Dong Hwang; Young-Jun Kim 001; Jun-Seok Park; Lee-Sup Kim (ISSCC, 2011)

A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications. - Mi-Jo Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Spread Spectrum Clock Generator for DisplayPort Main Link. - Won-Young Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Memory-Efficient Unified Early Z-Test. - Hong-Yun Kim; Chang-Hyo Yu; Lee-Sup Kim (IEEE Trans. Vis. Comput. Graph., 2011)

A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. - Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing. - Hyo-Eun Kim; Jun-Seok Park; Jae-Sung Yoon; Seok-Hoon Kim; Lee-Sup Kim (CICC, 2012)

PowerField: a transient temperature-to-power technique based on Markov random field theory. - Seungwook Paek; Seok-Hwan Moon; Wongyu Shin; Jaehyeong Sim; Lee-Sup Kim (DAC, 2012)

A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient. - Yong-Hun Kim; Lee-Sup Kim (ISCAS, 2012)

1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS. - Sang-Hye Chung; Lee-Sup Kim (VLSIC, 2012)

MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization. - Hong-Yun Kim; Young-Jun Kim 001; Lee-Sup Kim (IEEE J. Solid State Circuits, 2012)

A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme. - Won-Young Lee; Kyu-Dong Hwang; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. - Won-Young Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer. - Hyo-Eun Kim; Jae-Sung Yoon; Kyu-Dong Hwang; Young-Jun Kim 001; Jun-Seok Park; Lee-Sup Kim (IEEE Trans. Circuits Syst. Video Technol., 2012)

Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders. - Young-Jun Kim 001; Hyo-Eun Kim; Seok-Hoon Kim; Jun-Seok Park; Seungwook Paek; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider. - Seok-Hoon Kim; Sung-Eui Yoon; Sang-Hye Chung; Young-Jun Kim 001; Hong-Yun Kim; Kyusik Chung; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS. - Won-Young Lee; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 7 mW 2.5 GHz spread spectrum clock generator using switch-controlled injection-locked oscillator. - Jeongmin Yang; Young-Ju Kim 001; Lee-Sup Kim (ISCAS, 2013)

All-digital hybrid temperature sensor network for dense thermal monitoring. - Seungwook Paek; Wongyu Shin; Jaeyoung Lee; Hyo-Eun Kim; Jun-Seok Park; Lee-Sup Kim (ISSCC, 2013)

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. - Ji-Hwan Seol; Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Joo-Sun Choi; Lee-Sup Kim (ISSCC, 2013)

A 1 mJ/Frame Unified Media Application Processor With Dynamic Analog-Digital Mode Reconfiguration for Embedded 3D-Media Contents Processing. - Hyo-Eun Kim; Jun-Seok Park; Jae-Sung Yoon; Seok-Hoon Kim; Lee-Sup Kim (IEEE J. Solid State Circuits, 2013)

PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory. - Seungwook Paek; Wongyu Shin; Jaehyeong Sim; Lee-Sup Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process. - Kyu-Dong Hwang; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory. - Hong-Yun Kim; Young-Jun Kim 001; Jiehwan Oh; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD. - Won-Young Lee; Jiehwan Oh; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-µm CMOS Technology. - Jun-Seok Park; Hyo-Eun Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. Video Technol., 2013)

A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality. - Jae-Sung Yoon; Jeong-Hyun Kim; Hyo-Eun Kim; Won-Young Lee; Seok-Hoon Kim; Kyusik Chung; Jun-Seok Park; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

NUAT: A non-uniform access time memory controller. - Wongyu Shin; Jeongmin Yang; Jungwhan Choi; Lee-Sup Kim (HPCA, 2014)

Timing error masking by exploiting operand value locality in SIMD architecture. - Jaehyeong Sim; Jun-Seok Park; Seungwook Paek; Lee-Sup Kim (ICCD, 2014)

An area-efficient on-chip temperature sensor with nonlinearity compensation using injection-locked oscillator (ILO). - Wongyu Shin; Seungwook Paek; Lee-Sup Kim (ISCAS, 2014)

A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. - Sang-Hye Chung; Young-Ju Kim 001; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface. - Kyu-Dong Hwang; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS. - Young-Ju Kim 001; Sang-Hye Chung; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider. - Dongil Lee; Taeho Lee 001; Yong-Hun Kim; Young-Ju Kim 001; Lee-Sup Kim (CICC, 2015)

Multiple clone row DRAM: a low latency and area optimized DRAM. - Jungwhan Choi; Wongyu Shin; Jaemin Jang; Jinwoong Suh; Yongkee Kwon; Youngsuk Moon; Lee-Sup Kim (ISCA, 2015)

An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. - Daewoong Lee; Dongil Lee; Taeho Lee 001; Yong-Hun Kim; Lee-Sup Kim (ISCAS, 2015)

Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing. - Seungwook Paek; Wongyu Shin; Jaeyoung Lee; Hyo-Eun Kim; Jun-Seok Park; Lee-Sup Kim (IEEE J. Solid State Circuits, 2015)

A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. - Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS. - Sang-Hye Chung; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13 µm CMOS. - Young-Ju Kim 001; Sang-Hye Chung; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS. - Yong-Hun Kim; Young-Ju Kim 001; Tae-Ho Lee 001; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity. - Hoseok Seol; Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Lee-Sup Kim (ISCA, 2016)

Crosstalk avoidance code for direct pass-through architecture. - Minhye Kim; Soochang Chae; Young-Ju Kim 001; Seung-Jun Bae; Lee-Sup Kim (ISCAS, 2016)

14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems. - Jaehyeong Sim; Jun-Seok Park; Minhye Kim; Dongmyung Bae; Yeongjae Choi; Lee-Sup Kim (ISSCC, 2016)

Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. - Wongyu Shin; Jungwhan Choi; Jaemin Jang; Jinwoong Suh; Yongkee Kwon; Youngsuk Moon; Hongsik Kim; Lee-Sup Kim (IEEE Trans. Computers, 2016)

DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing. - Wongyu Shin; Jungwhan Choi; Jaemin Jang; Jinwoong Suh; Youngsuk Moon; Yongkee Kwon; Lee-Sup Kim (IEEE Trans. Computers, 2016)

A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS. - Sang-Hye Chung; Young-Ju Kim 001; Yong-Hun Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. - Dongil Lee; Taeho Lee 001; Young-Ju Kim 001; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm. - Jun-Seok Park; Hyo-Eun Kim; Hong-Yun Kim; Jaeyoung Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. Video Technol., 2016)

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method. - Yong-Hun Kim; Young-Ju Kim 001; Taeho Lee 001; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator. - Taeho Lee 001; Yong-Hun Kim; Jaehyeong Sim; Jun-Seok Park; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks. - Hyeonuk Kim; Jaehyeong Sim; Yeongjae Choi; Lee-Sup Kim (DAC, 2017)

SENIN: An energy-efficient sparse neuromorphic system with on-chip learning. - Myung-Hoon Choi; Seungkyu Choi; Jaehyeong Sim; Lee-Sup Kim (ISLPED, 2017)

Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph Cut in Resistor Grid. - Yeongjae Choi; Jun-Seok Park; Lee-Sup Kim (WACV, 2017)

Refresh-Aware Write Recovery Memory Controller. - Jaemin Jang; Wongyu Shin; Jungwhan Choi; Jinwoong Suh; Yongkee Kwon; Yongju Kim; Lee-Sup Kim (IEEE Trans. Computers, 2017)

Bank-Group Level Parallelism. - Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Lee-Sup Kim (IEEE Trans. Computers, 2017)

Rank-Level Parallelism in DRAM. - Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Yongkee Kwon; Youngsuk Moon; Lee-Sup Kim (IEEE Trans. Computers, 2017)

Energy-Efficient Design of Processing Element for Convolutional Neural Network. - Yeongjae Choi; Dongmyung Bae; Jaehyeong Sim; Seungkyu Choi; Minhye Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface. - Yong-Hun Kim; Taeho Lee 001; Hyun-Kyu Jeon; Dongil Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network. - Taeho Lee 001; Yong-Hun Kim; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

In-DRAM Data Initialization. - Hoseok Seol; Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

NID: processing binary convolutional neural network in commodity DRAM. - Jaehyeong Sim; Hoseok Seol; Lee-Sup Kim (ICCAD, 2018)

TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training. - Seungkyu Choi; Jaehyeong Sim; Myeonggu Kang; Lee-Sup Kim (ISLPED, 2018)

Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs. - Hoseok Seol; Wongyu Shin; Jaemin Jang; Jungwhan Choi; Hakseung Lee; Lee-Sup Kim (IEEE Trans. Computers, 2018)

A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. - Yong-Hun Kim; Dongil Lee; Daewoong Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. - Dongil Lee; Yong-Hun Kim; Daewoong Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices. - Seungkyu Choi; Jaehyeong Sim; Myeonggu Kang; Yeongjae Choi; Hyeonuk Kim; Lee-Sup Kim (A-SSCC, 2019)

An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices. - Seungkyu Choi; Jaekang Shin; Yeongjae Choi; Lee-Sup Kim (DAC, 2019)

NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks. - Hyeonuk Kim; Jaehyeong Sim; Yeongjae Choi; Lee-Sup Kim (HPCA, 2019)

eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators. - Youngbeom Jung; Yeongjae Choi; Jaehyeong Sim; Lee-Sup Kim (ICCAD, 2019)

An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM. - Kyeonghan Kim; Hyein Shin; Jaehyeong Sim; Myeonggu Kang; Lee-Sup Kim (ICCAD, 2019)

A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. - Hyein Shin; Jaehyeong Sim; Daewoong Lee; Lee-Sup Kim (ICCAD, 2019)

Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration. - Hyeonwook Wi; Hyeonuk Kim; Seungkyu Choi; Lee-Sup Kim (ISLPED, 2019)

A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. - Daewoong Lee; Dongil Lee; Yong-Hun Kim; Lee-Sup Kim (VLSI Circuits, 2019)

DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells. - Jungwhan Choi; Jaemin Jang; Lee-Sup Kim (IEEE Trans. Computers, 2019)

Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory. - Jaemin Jang; Wongyu Shin; Jungwhan Choi; Yongju Kim; Lee-Sup Kim (IEEE Trans. Computers, 2019)

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS. - Chongsoo Jung; Dongil Lee; Yong-Hun Kim; Daewoong Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. - Daewoong Lee; Dongil Lee; Yong-Hun Kim; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates. - Jaekang Shin; Seungkyu Choi; Yeongjae Choi; Lee-Sup Kim (DAC, 2020)

A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration. - Hyein Shin; Myeonggu Kang; Lee-Sup Kim (ICCAD, 2020)

An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices. - Seungkyu Choi; Jaehyeong Sim; Myeonggu Kang; Yeongjae Choi; Hyeonuk Kim; Lee-Sup Kim (IEEE J. Solid State Circuits, 2020)

CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator. - Yeongjae Choi; Jaehyeong Sim; Lee-Sup Kim (IEEE Trans. Circuits Syst., 2020)

A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. - Daewoong Lee; Dongil Lee; Yong-Hun Kim; Hyun-Kyu Jeon; Byung-Guk Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS. - Jaehyeong Sim; Somin Lee; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices. - Hyein Shin; Myeonggu Kang; Lee-Sup Kim (DAC, 2021)

Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator. - HanCheon Yun; Hyein Shin; Myeonggu Kang; Lee-Sup Kim (DAC, 2021)

A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation. - Seungkyu Choi; Jaekang Shin; Lee-Sup Kim (ICCAD, 2021)

A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators. - Myeonggu Kang; Hyein Shin; Jaekang Shin; Lee-Sup Kim (ICCAD, 2021)

Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity. - Kangkyu Park; Yunki Han; Lee-Sup Kim (ICCAD, 2021)

Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks. - Hoseok Seol; Minhye Kim; Taesoo Kim; Yongdae Kim; Lee-Sup Kim (IEEE Trans. Computers, 2021)

Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNN. - Jaekang Shin; Seungkyu Choi; Jongwoo Ra; Lee-Sup Kim (DAC, 2022)

Re2fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN Accelerators. - Hyein Shin; Myeonggu Kang; Lee-Sup Kim (ICCAD, 2022)

A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type. - Seungkyu Choi; Jaekang Shin; Lee-Sup Kim (IEEE Trans. Computers, 2022)

EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access. - Yunki Han; Kangkyu Park; Youngbeom Jung; Lee-Sup Kim (IEEE Trans. Computers, 2022)

S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity. - Myeonggu Kang; Hyeonuk Kim; Hyein Shin; Jaehyeong Sim; Kyeonghan Kim; Lee-Sup Kim (IEEE Trans. Computers, 2022)

Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks. - Kangkyu Park; Seungkyu Choi; Yeongjae Choi; Lee-Sup Kim (IEEE Trans. Computers, 2022)

A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture. - Myeonggu Kang; Hyein Shin; Lee-Sup Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Quantization-Error-Robust Deep Neural Network for Embedded Accelerators. - Youngbeom Jung; Hyeonuk Kim; Yeongjae Choi; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing. - Junkyum Kim; Myeonggu Kang; Yunki Han; Yanggon Kim; Lee-Sup Kim (HPCA, 2023)

Energy-Efficient CNN Personalized Training by Adaptive Data Reformation. - Youngbeom Jung; Hyeonuk Kim; Seungkyu Choi; Jaekang Shin; Lee-Sup Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor. - Seungkyu Choi; Jaekang Shin; Lee-Sup Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators. - Hyein Shin; Myeonggu Kang; Lee-Sup Kim (IEEE Trans. Computers, 2023)

MGen: A Framework for Energy-Efficient In-ReRAM Acceleration of Multi-Task BERT. - Myeonggu Kang; Hyein Shin; Junkyum Kim; Lee-Sup Kim (IEEE Trans. Computers, 2023)

Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation. - Junyoung Park; Myeonggu Kang; Yunki Han; Yanggon Kim; Jaekang Shin; Lee-Sup Kim (DAC, 2024)

CoCoA: Algorithm-Hardware Co-Design for Large-Scale GNN Training using Compressed Graph. - Yunki Han; Jaekang Shin; Gunhee Park; Lee-Sup Kim (ICCAD, 2024)

Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications. - Yanggon Kim; Yunki Han; Jaekang Shin; Junkyum Kim; Lee-Sup Kim (IEEE Comput. Archit. Lett., 2024)

ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks. - Hyeonuk Kim; Youngbeom Jung; Lee-Sup Kim (IEEE Trans. Computers, 2024)

ToEx: Accelerating Generation Stage of Transformer-Based Language Models via Token-Adaptive Early Exit. - Myeonggu Kang; Junyoung Park; Hyein Shin; Jaekang Shin; Lee-Sup Kim (IEEE Trans. Computers, 2024)

EOD: Enabling Low Latency GNN Inference via Near-Memory Concatenate Aggregation. - Taehwan Kim; Yunki Han; Seohye Ha; Jiwan Kim; Lee-Sup Kim (ISCA, 2025)

AToM: Adaptive Token Merging for Efficient Acceleration of Vision Transformer. - Jaekang Shin; Myeonggu Kang; Yunki Han; Junyoung Park; Lee-Sup Kim (IEEE Trans. Computers, 2025)