Simulating pass transistor circuits using logic simulation machines. - Zeev Barzilai; Leendert M. Huisman; Gabriel M. Silberman; Donald T. Tang; Lin S. Woo (DAC, 1983)

Fast Pass-Transistor Simulation for Custom MOS Circuits. - Zeev Barzilai; Leendert M. Huisman; Gabriel M. Silberman; Donald T. Tang; Lin S. Woo (IEEE Des. Test, 1984)

Using a Hardware Simulation Engine for Custom MOS Structured Designs. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Gabriel M. Silberman (IBM J. Res. Dev., 1984)

SLS - a fast switch level simulator for verification and fault coverage analysis. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (DAC, 1986)

The reliability of approximate testability measures. - Leendert M. Huisman (IEEE Des. Test, 1988)

SLS-a fast switch-level simulator [for MOS]. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

TRIM: testability range by ignoring the memory. - Larry Carter; Leendert M. Huisman; Tom W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Fault simulation of logic designs on parallel processors with distributed memory. - Leendert M. Huisman; Raja Daoud (ITC, 1990)

Symbolic implication in test generation. - Sandip Kundu; Indira Nair; Leendert M. Huisman; Vijay S. Iyengar (EURO-DAC, 1991)

A Small Test Generator for Large Designs. - Sandip Kundu; Leendert M. Huisman; Indira Nair; Vijay S. Iyengar; Lakshmi N. Reddy (ITC, 1992)

The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. - Peter C. Maxwell; Robert C. Aitken; Leendert M. Huisman (ITC, 1994)

Highly Reliable Symmetric Networks. - Leendert M. Huisman; Sandip Kundu (IEEE Trans. Parallel Distributed Syst., 1994)

Yield fluctuations and defect models. - Leendert M. Huisman (J. Electron. Test., 1995)

Correlations between path delays and the accuracy of performance prediction. - Leendert M. Huisman (ITC, 1998)

Diagnosis and characterization of timing-related defects by time-dependent light emission. - Daniel R. Knebel; Pia N. Sanda; Moyra K. McManus; Jeffrey A. Kash; James C. Tsang; David P. Vallett; Leendert M. Huisman; Phil Nigh; Rick Rizzolo; Peilin Song; Franco Motika (ITC, 1998)

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. - Thomas Bartenstein; Douglas Heaberlin; Leendert M. Huisman; David Sliwinski (ITC, 2001)

Analysis and Design of Optimal Combinational Compactors. - Peter Wohl; Leendert M. Huisman (VTS, 2003)

Data Mining Integrated Circuit Fails with Fail Commonalities. - Leendert M. Huisman; Maroun Kassab; Leah Pastel (ITC, 2004)

Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). - Leendert M. Huisman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)