Real-time frame-straddling-based optical flow detection. - Lei Chen 001; Hua Yang; Takeshi Takaki; Idaku Ishii (ROBIO, 2011)

Accuracy of Gradient-Based Optical Flow Estimation in High-Frame-Rate Video Analysis. - Lei Chen 001; Takeshi Takaki; Idaku Ishii (IEICE Trans. Inf. Syst., 2012)

Real-Time Optical Flow Estimation Using Multiple Frame-Straddling Intervals. - Lei Chen 001; Hua Yang; Takeshi Takaki; Idaku Ishii (J. Robotics Mechatronics, 2012)

LVQ neural network SoC adaptable to different on-chip learning and recognition applications. - Fengwei An; Toshinobu Akazawa; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (APCCAS, 2014)

A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability. - Fengwei An; Toshinobu Akazawa; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (CICC, 2014)

A SoPC architecture for nearest-neighbor based learning and recognition. - Fengwei An; Lei Chen 001; Hans Jürgen Mattausch (ISPACS, 2014)

Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. - Fengwei An; Keisuke Mihara; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (A-SSCC, 2015)

Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators. - Tapas Kumar Maiti; Lei Chen 001; Hidenori Miyamoto; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (ESSDERC, 2015)

Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. - Yuki Fujita; Fengwei An; Aiwen Luo; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (APCCAS, 2016)

Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (ISCAS, 2016)

k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching. - Fengwei An; Lei Chen 001; Toshinobu Akazawa; Shogo Yamazaki; Hans Jürgen Mattausch (IEICE Trans. Electron., 2016)

Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump. - Lei Chen 001; Tapas Kumar Maiti; Hidenori Miyamoto; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Multi Scale Comput. Syst., 2016)

Object-recognition VLSI for pedestrian detection in automotive applications. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Idaku Ishii (ASICON, 2017)

A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor. - Zunkai Huang; Xiangyu Zhang 002; Lei Chen 001; Yongxin Zhu 001; Fengwei An; Hui Wang 036; Songlin Feng (IEEE Access, 2017)

Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. - Jungang Guan; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (Sensors, 2017)

A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. - Xiangyu Zhang 002; Fengwei An; Lei Chen 001; Idaku Ishii; Hans Jürgen Mattausch (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. - Fengwei An; Xiangyu Zhang 002; Aiwen Luo; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Circuits Syst. Video Technol., 2018)

Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. - Aiwen Luo; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. - Jungang Guan; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2019)

A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices. - Peng Xu; Zhihua Xiao; Xianglong Wang; Lei Chen 001; Chao Wang 096; Fengwei An (Sensors, 2020)

A Multi-Class Objects Detection Coprocessor With Dual Feature Space and Weighted Softmax. - Zhihua Xiao; Peng Xu; Xianglong Wang; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

FPGA-Based Low-Visibility Enhancement Accelerator for Video Sequence by Adaptive Histogram Equalization With Dynamic Clip-Threshold. - Canran Xu; Zizhao Peng; Xuanzhen Hu; Wei Zhang; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst., 2020)

A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching. - Pingcheng Dong; Zhuoao Li; Zhuoyu Chen; Ruoheng Yao; Huanshihong Deng; Wenyue Zhang; Yangyi Zhang; Lei Chen 001; Chao Wang 096; Fengwei An (A-SSCC, 2021)

A Pseudo 943 million Frames Per Rate High-Speed Camera with Asynchronous Double-Frame Exposure for Motion Estimation. - Ruoheng Yao; Huanshihong Deng; Wenyue Zhang; Yangyi Zhang; Lei Chen 001; Fengwei An (ICTA, 2021)

Efficient VLSI Architecture for Edge Sensing Anti-Aliasing Demosaicing. - Yangyi Zhang; Zizhao Peng; Ruoheng Yao; Huanshihong Deng; Wenyue Zhang; Lei Chen 001; Fengwei An (ICTA, 2021)

Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm. - Zhuoyu Chen; Pingcheng Dong; Zhuoao Li; Ruoheng Yao; Yunhao Ma; Xiwei Fang; Huanshihong Deng; Wenyue Zhang; Lei Chen 001; Fengwei An (SoCC, 2021)

Subpixel Interpolation Disparity Refinement for Semi-Global Matching. - Yunhao Ma; Xiwei Fang; Pingcheng Dong; Xinyu Guan; Ke Li; Lei Chen 001; Fengwei An (APCCAS, 2022)

A Dynamic JPEG CODEC with Adaptive Quantization Table for Frame Storage Compression. - Yichen Ouyang; Xianglong Wang; Gang Shi; Lei Chen 001; Fengwei An (APCCAS, 2022)

A 14.39ppm/kPa Stress Sensor with Low Temperature-drift and High Linearity for turbulence Stress. - Lanxiang Xiao; Lei Chen 001; Fengwei An (ICTA, 2022)

Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA. - Yunhao Ma; Xiwei Fang; Pingcheng Dong; Xinyu Guan; Ke Li; Lei Chen 001; Fengwei An (SOCC, 2022)

Lane Departure Assessment via Enhanced Single Lane-Marking. - Yiwei Luo; Ping Li 016; Gang Shi; Zuowei Liang; Lei Chen 001; Fengwei An (Sensors, 2022)

Five-Direction Occlusion Filling with Five Layer Parallel Two-Stage Pipeline for Stereo Matching with Sub-Pixel Disparity Map Estimation. - Yunhao Ma; Xiwei Fang; Xinyu Guan; Ke Li; Lei Chen 001; Fengwei An (Sensors, 2022)

A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application. - Pingcheng Dong; Zhuoyu Chen; Zhuoao Li; Yuzhe Fu; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Configurable Image Rectification and Disparity Refinement for Stereo Vision. - Pingcheng Dong; Zhuoyu Chen; Zhuoao Li; Ruoheng Yao; Wenyue Zhang; Yangyi Zhang; Lei Chen 001; Chao Wang 096; Fengwei An (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Compact Hardware Architecture for Bilateral Filter With the Combination of Approximate Computing and Look-Up Table. - Ruoheng Yao; Lei Chen 001; Pingcheng Dong; Zhuoyu Chen; Fengwei An (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Asynchronous Double-Frame-Exposure Binocular-Camera With Pixel-Level Pipeline Architecture for High-Speed Motion Tracking. - Ruoheng Yao; Huanshihong Deng; Wengyue Zhang; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Live Demonstration: Supervised-learning-based Visual Quantification for Image Enhancement. - Wei Zhang; Junfeng Chang; Zizhao Peng; Lei Chen 001; Fengwei An (AICAS, 2023)

A Dynamic Codec with Adaptive Quantization for Convolution Neural Network. - Yichen Ouyang; Xianglong Wang; Gang Shi; Lei Chen 001; Fengwei An (ASICON, 2023)

A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Pico Aerial Vehicles. - Pingcheng Dong; Zhuoyu Chen; Ke Li; Lei Chen 001; Kwang-Ting Cheng; Fengwei An (ESSCIRC, 2023)

A Non-Local Means Denoising Co-Processor with Data Reuse Scheme and Dual-Clock Domain for High Resolution Image Sensor. - Zhiyue Gao; Fengwei An; Lei Chen 001 (ICTA, 2023)

An 11.6aF/kPa Mechanical Stress Sensor With 0.808% Temperature-Drift Oscillator for Flip-Chip Packaging. - Lanxiang Xiao; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Spatio-Temporal Video Denoising Co-Processor With Adaptive Codec. - Gang Shi; Xianglong Wang; Yichen Ouyang; Ruoheng Yao; Zhuoyu Chen; Wei Zhang; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Live Demonstration: A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Low-power Applications. - Zhuoyu Chen; Shengming Zhou; Pingcheng Dong; Ke Li; Wenyue Zhang; Fengwei An; Lei Chen 001 (ISCAS, 2024)

Stereo Matching Accelerator With Re-Computation Scheme and Data-Reused Pipeline for Autonomous Vehicles. - Ke Li; Xiwei Fang; Yunhao Ma; Wenyue Zhang; Pingcheng Dong; Zhuoyu Chen; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Min-Pooling Cost Aggregation for Semi-Global Matching of Stereo Vision Processor. - Wenyue Zhang; Pingcheng Dong; Lei Chen 001; Zhengyu Ma; Fengwei An (IEEE Trans. Circuits Syst. II Express Briefs, 2025)