A novel configurable no dead-zone digital phase detector design. - Min Wang; Zhiping Wen 001; Lei Chen 010; Yanlong Zhang (APCCAS, 2008)

BIST approach for testing configurable logic and memory resources in FPGAs. - Zhiquan Zhang; Zhiping Wen 001; Lei Chen 010; Tao Zhou; Fan Zhang (APCCAS, 2008)

A novel BIST approach for testing input/output buffers in FPGAs. - Lei Chen 010; Zhiquan Zhang; Zhiping Wen 001 (FPGA, 2009)

A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA. - Lei Wang 003; Lei Chen 010; Zhiping Wen 001; Huabo Sun; Shuo Wang (ReConFig, 2009)

Study of an Automated Precise SEU Fault Injection Technique. - Jing Zhou; Zengrong Liu; Lei Chen 010; Shuo Wang; Zhiping Wen 001; Lishuai Wu; Xun Chen (IPDPS Workshops, 2012)

An accurate fault location method based on configuration bitstream analysis. - Jing Zhou; Zengrong Liu; Lei Chen 010; Shuo Wang; Zhiping Wen 001; Xun Chen; Chang Qi (NORCHIP, 2012)

Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only). - Jing Zhou; Lei Chen 010; Shuo Wang (FPGA, 2013)

A configurable fault-tolerant glitch-free clock switching circuit. - Haochi Wang; Yanlong Zhang; Xuewu Li; Lei Chen 010; Zhiping Wen 001; Kun Zhang; Min Wang (MWSCAS, 2013)

Coordinating routing resources for hex pips test in island-style FPGAs (abstract only). - Fan Zhang; Lei Chen 010; Wenyao Xu; Yuanfu Zhao; Zhiping Wen 001 (FPGA, 2014)

300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only). - Lei Chen 010; Yuanfu Zhao; Zhiping Wen 001; Jing Zhou; Xuewu Li; Yanlong Zhang; Huabo Sun (FPGA, 2015)

A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only). - Xianjian Zheng; Fan Zhang; Lei Chen 010; Zhiping Wen 001; Yuanfu Zhao; Xuewu Li (FPGA, 2015)

A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology. - Yong Fu; Zhiping Wen 001; Lei Chen 010 (ICCIP, 2016)

Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA. - Tingting Yu; Lei Chen 010; Xuewu Li; Shuo Wang; Jing Zhou (IEEA, 2017)

Research on agile FPGA fault injection system. - Yaowei Zhang; Lei Chen 010; Shuo Wang; Jing Zhou; Chunsheng Tian; Hanxu Feng (ICM, 2021)

Post-silicon Trace Signal Selection Using Genetic Algorithm. - Hanxu Feng; Yuanhang Bu; Jing Zhou; Shuo Wang; Zhuoli Wang; Lei Chen 010 (ATS, 2024)