Lei He
Orcid: 0000-0002-5266-3805Affiliations:
- University of California, Los Angeles, Department of Electrical Engineering, CA, USA
- University of Wisconsin, Madison, WI, USA (1999 - 2002)
According to our database1,
Lei He
authored at least 268 papers
between 1996 and 2023.
Collaborative distances:
Collaborative distances:
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on ee.ucla.edu
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Bibliography
2023
ACM Trans. Reconfigurable Technol. Syst., March, 2023
Progressive Energy-Based Cooperative Learning for Multi-Domain Image-to-Image Translation.
CoRR, 2023
CoRR, 2023
MDT-Net: Multi-Domain Transfer by Perceptual Supervision for Unpaired Images in OCT Scan.
Proceedings of the 20th IEEE International Symposium on Biomedical Imaging, 2023
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023
2022
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration.
ACM Trans. Reconfigurable Technol. Syst., 2022
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation.
ACM Trans. Design Autom. Electr. Syst., 2022
Effective Scaling of Blockchain Beyond Consensus Innovations and Moore's Law: Challenges and Opportunities.
IEEE Syst. J., 2022
An IoT-based intelligent irrigation system with data fusion and a self-powered wide-area network.
J. Ind. Inf. Integr., 2022
BCmaster: A Compatible Framework for Comprehensively Analyzing and Monitoring Blockchain Systems in IoT.
IEEE Internet Things J., 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
ReMix: A General and Efficient Framework for Multiple Instance Learning Based Whole Slide Image Classification.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2022, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
ConCL: Concept Contrastive Learning for Dense Prediction Pre-training in Pathology Images.
Proceedings of the Computer Vision - ECCV 2022, 2022
2021
IEEE Trans. Wirel. Commun., 2021
Future Gener. Comput. Syst., 2021
OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray.
CoRR, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
TumorCP: A Simple but Effective Object-Level Data Augmentation for Tumor Segmentation.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2021 - 24th International Conference, Strasbourg, France, September 27, 2021
OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray.
Proceedings of the IUI '21: 26th International Conference on Intelligent User Interfaces, 2021
Proceedings of the 18th IEEE International Symposium on Biomedical Imaging, 2021
T-Net: Learning Feature Representation With Task-Specific Supervision For Biomedical Image Analysis.
Proceedings of the 18th IEEE International Symposium on Biomedical Imaging, 2021
MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
Robust Beamforming Design for Correlated MISO Wiretap Channels Under Channel Uncertainty.
IEEE Wirel. Commun. Lett., 2020
IEEE Wirel. Commun. Lett., 2020
Correlation-Based Cooperative Jamming to Enhance Secrecy With Receiver-Side Correlation.
IEEE Trans. Veh. Technol., 2020
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
QoS-Based Robust Cooperative-Jamming-Aided Beamforming for Correlated Wiretap Channels.
IEEE Signal Process. Lett., 2020
Oral-3D: Reconstructing the 3D Bone Structure of Oral Cavity from 2D Panoramic X-ray.
CoRR, 2020
T-Net: A Template-Supervised Network for Task-specific Feature Extraction in Biomedical Image Analysis.
CoRR, 2020
CoRR, 2020
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2020, 2020
A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
OralCam: Enabling Self-Examination and Awareness of Oral Health Using a Smartphone Camera.
Proceedings of the CHI '20: CHI Conference on Human Factors in Computing Systems, 2020
Proceedings of The 12th Asian Conference on Machine Learning, 2020
2019
IEEE Trans. Wirel. Commun., 2019
IEEE Commun. Lett., 2019
CoRR, 2019
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2019, 2019
Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis.
Proceedings of the 2019 International Symposium on Physical Design, 2019
Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2019
Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Probabilistic Model Checking and Scheduling Implementation of an Energy Router System in Energy Internet for Green Cities.
IEEE Trans. Ind. Informatics, 2018
IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications - Part II.
IEEE Access, 2018
IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications.
IEEE Access, 2018
Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
A fast and robust failure analysis of memory circuits using adaptive importance sampling method.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEICE Electron. Express, 2017
Asia Pac. J. Oper. Res., 2017
Modeling and Implementation of Electroactive Smart Air-Conditioning Vent Register for Personalized HVAC Systems.
IEEE Access, 2017
Proceedings of the 2017 IEEE Global Communications Conference, 2017
Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Sampling and Reconstruction in Arbitrary Measurement and Approximation Spaces Associated With Linear Canonical Transform.
IEEE Trans. Signal Process., 2016
Proceedings of the 16th IEEE International Working Conference on Source Code Analysis and Manipulation, 2016
Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage.
Proceedings of the 2016 on International Symposium on Physical Design, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IEEE Trans. Ind. Informatics, 2015
An improved spray and wait algorithm based on RVNS in Delay Tolerant Mobile Sensor Networks.
Proceedings of the 2015 IEEE International Conference on Communications, 2015
A Social Awareness based Feedback Mechanism for delivery reliability in Delay Tolerant Networks.
Proceedings of the 2015 IEEE International Conference on Communications, 2015
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Integr., 2014
Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges.
IEEE Des. Test, 2014
Accelerating the iterative linear solver for reservoir simulation on multicore architectures.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty.
Integr., 2013
Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms.
IEEE Des. Test, 2013
Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2013
2012
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Reconfigurable Technol. Syst., 2012
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.
ACM Trans. Design Autom. Electr. Syst., 2012
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials.
ACM Trans. Design Autom. Electr. Syst., 2012
IEEE Trans. Inf. Technol. Biomed., 2012
Proceedings of the 5th International Conference on PErvasive Technologies Related to Assistive Environments, 2012
Proceedings of the International Symposium on Physical Design, 2012
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
2011
Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Found. Trends Electron. Des. Autom., 2011
Proceedings of the 2011 International Symposium on Physical Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials.
Proceedings of the 48th Design Automation Conference, 2011
2010
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling.
IEEE Trans. Very Large Scale Integr. Syst., 2010
EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2010
ACM Trans. Design Autom. Electr. Syst., 2010
Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
QuickYield: an efficient global-search based parametric yield estimation with performance constraints.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Des. Test Comput., 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Symposium on Physical Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.
Proceedings of the 46th Design Automation Conference, 2009
Incremental and on-demand random walk for iterative power distribution network analysis.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.
ACM Trans. Design Autom. Electr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L<sub>eff</sub> Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
Proceedings of the 2007 International Symposium on Physical Design, 2007
Empire: an efficient and compact multiple-parameterized model order reduction method.
Proceedings of the 2007 International Symposium on Physical Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Temperature aware microprocessor floorplanning considering application dependent power load.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Modeling and synthesis of multiport transmission line for multichannel communication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 International Symposium on Physical Design, 2006
SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance.
Proceedings of the 2006 International Symposium on Physical Design, 2006
Proceedings of the 2006 International Symposium on Physical Design, 2006
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
A fast block structure preserving model order reduction for inverse inductance circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Fast analysis of structured power grid by triangularization based structure preserving model order reduction.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Circuits and architectures for field programmable gate array with configurable supply voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Temperature and supply Voltage aware performance and power modeling at microarchitecture level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
J. Low Power Electron., 2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.
Proceedings of the 2005 International Symposium on Physical Design, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
A sparsified vector potential equivalent circuit model for massively coupled interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.
ACM Trans. Design Autom. Electr. Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 2004 International Symposium on Physical Design, 2004
Shielding area optimization under the solution of interconnect crosstalk.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Performance and RLC crosstalk driven global routing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
System level leakage reduction considering the interdependence of temperature and leakage.
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003
Microarchitecture level power and thermal simulation considering temperature dependent leakage model.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
Proceedings of the 40th Design Automation Conference, 2003
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.
Proceedings of the 2000 International Symposium on Physical Design, 2000
Proceedings of the 2000 Design, 2000
1999
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
An efficient technique for device and interconnect optimization in deep submicron designs.
Proceedings of the 1998 International Symposium on Physical Design, 1998
1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.
Proceedings of the 34st Conference on Design Automation, 1997
1996
ACM Trans. Design Autom. Electr. Syst., 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996