Lei Jiang

According to our database1, Lei Jiang authored at least 41 papers between 2008 and 2019.

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Bibliography

2019
HolyLight: A Nanophotonic Accelerator for Deep Learning in Data Centers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Thermal Sensing Using Micro-ring Resonators in Optical Network-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Fault-Tolerant Neural Network Architecture.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs.
Computer Architecture Letters, 2018

BRAWL: A Spintronics-Based Portable Basecalling-in-Memory Architecture for Nanopore Genome Sequencing.
Computer Architecture Letters, 2018

Performance Characterization of Multi-threaded Graph Processing Applications on Many-Integrated-Core Architecture.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

3DICT: a reliable and QoS capable mobile process-in-memory architecture for lookup-based CNNs in 3D XPoint ReRAMs.
Proceedings of the International Conference on Computer-Aided Design, 2018

Repurposing SoC analog circuitry for additional COTS hardware security.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

DeepN-JPEG: a deep neural network favorable JPEG-based image compression framework.
Proceedings of the 55th Annual Design Automation Conference, 2018

DrAcc: a DRAM based accelerator for accurate CNN inference.
Proceedings of the 55th Annual Design Automation Conference, 2018

PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learning.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.
ACM Trans. Embedded Comput. Syst., 2017

Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication.
Computer Architecture Letters, 2017

High-Performance Massive Subgraph Counting Using Pipelined Adaptive-Group Communication.
Proceedings of the Big Data and HPC: Ecosystem and Convergence, TopHPC 2017, 2017

Constructing fast and energy efficient 1TnR based ReRAM crossbar memory.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change Memories.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A statistical STT-RAM retention model for fast memory subsystem designs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Benchmarking Harp-DAAL: High Performance Hadoop on KNL Clusters.
Proceedings of the 2017 IEEE 10th International Conference on Cloud Computing (CLOUD), 2017

2016
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology.
ACM Trans. Design Autom. Electr. Syst., 2015

Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
A low power and reliable charge pump design for Phase Change Memories.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Mitigating Write Disturbance in Super-Dense Phase Change Memories.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

SLC-enabled Wear Leveling for MLC PCM Considering Process Variation.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory.
TACO, 2013

Compiler directed write-mode selection for high performance low power volatile PCM.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

2012
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

ER: elastic RESET for low power and long endurance MLC based phase change memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Improving write operations in MLC phase change memory.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory.
Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

2010
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2010

2008
Pre-synthesis resource generation and estimation for transport-triggered architecture (TTA)-like architecture.
Microprocessors and Microsystems - Embedded Hardware Design, 2008


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