Lei Jin

According to our database, Lei Jin authored at least 9 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse.

Lei Jin, Sangyeun Cho

IEEE Trans. Computers, 2011

2010

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach.

Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho

Softw. Pract. Exp., 2010

2009

SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors.

Lei Jin, Sangyeun Cho

Proceedings of the PACT 2009, 2009

2008

Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches.

Lei Jin, Sangyeun Cho

Proceedings of the 2008 International Conference on Parallel Processing, 2008

TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation.

Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng

Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007

Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems.

Sangyeun Cho, Lei Jin, Kiyeon Lee

Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

2006

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation.

Sangyeun Cho, Lei Jin

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Reducing cache traffic and energy with macro data load.

Lei Jin, Sangyeun Cho

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A flexible data to L2 cache mapping approach for future multicore processors.

Lei Jin, Hyunjin Lee, Sangyeun Cho

Proceedings of the 2006 workshop on Memory System Performance and Correctness, 2006