A flexible data to L2 cache mapping approach for future multicore processors. - Lei Jin 002; Hyunjin Lee; Sangyeun Cho (Memory System Performance and Correctness, 2006)

Reducing cache traffic and energy with macro data load. - Lei Jin 002; Sangyeun Cho (ISLPED, 2006)

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. - Sangyeun Cho; Lei Jin 002 (MICRO, 2006)

Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. - Sangyeun Cho; Lei Jin 002; Kiyeon Lee (RTCSA, 2007)

TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. - Sangyeun Cho; Socrates Demetriades; Shayne Evans; Lei Jin 002; Hyunjin Lee; Kiyeon Lee; Michael Moeng (ICPP, 2008)

Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches. - Lei Jin 002; Sangyeun Cho (ICPP, 2008)

SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. - Lei Jin 002; Sangyeun Cho (PACT, 2009)

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. - Hyunjin Lee; Lei Jin 002; Kiyeon Lee; Socrates Demetriades; Michael Moeng; Sangyeun Cho (Softw. Pract. Exp., 2010)

Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse. - Lei Jin 002; Sangyeun Cho (IEEE Trans. Computers, 2011)