Lei Zhang

Orcid: 0000-0001-9711-8758

Affiliations:

Chinese Academy of Sciences, Institute of Computing Technology, Research Center for Ubiquitous Computing Systems, Beijing, China
Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China (PhD 2008)

According to our database¹, Lei Zhang authored at least 79 papers between 2007 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2023

Soft Error Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Network Pruning for Bit-Serial Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

S$^{2}$ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., March, 2023

A Framework for Neural Network Architecture and Compile Co-optimization.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2023

Optimus: An Operator Fusion Framework for Deep Neural Networks.

[BibT_eX]

[DOI]

Xuyi Cai

Ying Wang

Lei Zhang

ACM Trans. Embed. Comput. Syst., 2023

IVP: An Intelligent Video Processing Architecture for Video Streaming.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2023

Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance.

[BibT_eX]

[DOI]

CoRR, 2023

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

Variation Enhanced Attacks Against RRAM-based Neuromorphic Computing System.

[BibT_eX]

[DOI]

CoRR, 2023

Efficient Supernet Training Using Path Parallelism.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Olympus: Reaching Memory-Optimality on DNN Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Winograd convolution: a perspective from fault tolerance.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Processing-in-SRAM acceleration for ultra-low power visual 3D perception.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

CHaNAS: coordinated search for network architecture and scheduling policy.

[BibT_eX]

[DOI]

Proceedings of the LCTES '21: 22nd ACM SIGPLAN/SIGBED International Conference on Languages, 2021

Optimus: towards optimal layer-fusion on deep learning processors.

[BibT_eX]

[DOI]

Xuyi Cai

Ying Wang

Lei Zhang

Proceedings of the LCTES '21: 22nd ACM SIGPLAN/SIGBED International Conference on Languages, 2021

NASA: Accelerating Neural Network Design with a NAS Processor.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Automation, 2021

MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Tenet: A Neural Network Model Extraction Attack in Multi-core Architecture.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

An Intelligent Video Processing Architecture for Edge-cloud Video Streaming.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Multi-task Scheduling for PIM-based Heterogeneous Computing System.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Towards Best-effort Approximation: Applying NAS to General-purpose Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

BitPruner: Network Pruning for Bit-serial Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Addressing Sparsity in Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Ecosystem of Things: Hardware, Software, and Architecture.

[BibT_eX]

[DOI]

Proc. IEEE, 2019

Correlation of Gut Microbiome Between ASD Children and Mothers and Potential Biomarkers for Risk Assessment.

[BibT_eX]

[DOI]

Genom. Proteom. Bioinform., 2019

Modeling of Mixing Uniformity for Food With Special Medicinal Purposes Based on Chinese Herbal Medicine.

[BibT_eX]

[DOI]

IEEE Access, 2019

OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Resilient Neural Network Training for Accelerators with Computing Errors.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

BenchIP: Benchmarking Intelligence Processors.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2018

2017

BENCHIP: Benchmarking Intelligence Processors.

[BibT_eX]

[DOI]

CoRR, 2017

The Φ-stack for smart web of things.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Smart Internet of Things, SmartIoT@SEC 2017, 2017

2016

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Cambricon-X: An accelerator for sparse neural networks.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015

Data Remapping for Static NUCA in Degradable Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Economizing TSV Resources in 3-D Network-on-Chip Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Neuromorphic accelerators: a comparison between neuroscience and machine-learning approaches.

[BibT_eX]

[DOI]

Zidong Du

Daniel D. Ben-Dayan Rubin

Proceedings of the 48th International Symposium on Microarchitecture, 2015

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

An Elastic Architecture Adaptable to Various Application Scenarios.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2014

Reinventing Memory System Design for Many-Accelerator Architecture.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2014

A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2014

2013

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

2012

An Elastic Architecture Adaptable to Millions of Application Scenarios.

[BibT_eX]

[DOI]

Proceedings of the Network and Parallel Computing, 9th IFIP International Conference, 2012

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A greedy approach to tolerate defect cores for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Flex memory: Exploiting and managing abundant off-chip optical bandwidth.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Wear rate leveling: lifetime enhancement of PRAM with endurance variation.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

A resilient on-chip router design through data path salvaging.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A teleoperation system for mobile robot with whole viewpoints virtual scene for situation awareness.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2008

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

A Routing Algorithm for Random Error Tolerance in Network-on-Chip.

[BibT_eX]

[DOI]

Lei Zhang

Huawei Li

Xiaowei Li

Proceedings of the Human-Computer Interaction. HCI Applications and Services, 2007

Lei Zhang

Timeline

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Online presence:

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Bibliography

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